cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
behdad18
Visitor
Visitor
532 Views
Registered: ‎01-18-2021

Cannot set IO voltages on Pynq-Z2 to 1.8V

Jump to solution

Hello, I have Pynq-Z2 eval board which I'm using to characterize my test chip. The Chip works with 1.8V IO voltage so I configured all the IO banks I'm using to 1.8V in Vivado but when implementing on FPGA everything is in 3.3V. I read the implementation report and it correctly mentions all banks are in 1.8V. Not sure what I'm doing wrong here?

I'm very new to FPGA so any help is very much appreciated. Thanks!

0 Kudos
1 Solution

Accepted Solutions
517 Views
Registered: ‎01-22-2015

@behdad18 

Welcome to the Forum!

The schematic for the Pynq-Z2 board shows that all the PL-side banks (13, 34, 35) have VCCO = 3.3V.  So, in Vivado you must use IOSTANDARDs that are compatible with this value of VCCO.   You cannot use commands/constraints in Vivado to change the values of VCCO on the Pynq-Z2 board.

It is possible to tell Vivado that VCCO=1.8V for the PL-side banks (13, 34, 35), but this is both wrong and dangerous - because you could damage the FPGA.   

Please refer to Table 1-55 in in UG471(v1.10) to determine which IOSTANDARDs can be used with VCCO = 3.3V.

Cheers,
Mark

View solution in original post

4 Replies
518 Views
Registered: ‎01-22-2015

@behdad18 

Welcome to the Forum!

The schematic for the Pynq-Z2 board shows that all the PL-side banks (13, 34, 35) have VCCO = 3.3V.  So, in Vivado you must use IOSTANDARDs that are compatible with this value of VCCO.   You cannot use commands/constraints in Vivado to change the values of VCCO on the Pynq-Z2 board.

It is possible to tell Vivado that VCCO=1.8V for the PL-side banks (13, 34, 35), but this is both wrong and dangerous - because you could damage the FPGA.   

Please refer to Table 1-55 in in UG471(v1.10) to determine which IOSTANDARDs can be used with VCCO = 3.3V.

Cheers,
Mark

View solution in original post

behdad18
Visitor
Visitor
481 Views
Registered: ‎01-18-2021

Thanks Mark, that was actually very helpful! I apologize if this is not a right place to ask but do you have any suggestion as what kind of eval board I should use that has 1.8V IO. I need around 40 GPIOs. Thank you!

0 Kudos
432 Views
Registered: ‎01-22-2015

@behdad18 

...do you have any suggestion as what kind of eval board I should use that has 1.8V IO. I need around 40 GPIOs

Since you mentioned Vivado and 1.8V IO then I assume you need about 40 high-performance GPIO from a conventional FPGA.  

Xilinx FPGAs have IO banks that are usually classified as either High-Performance(HP) or High-Range(HR).  Most boards will use VCCO=1.8V for HP banks and VCCO=3.3V for HR banks.  

Xilinx FPGAs can have all HR banks (eg. Artix-7), a mixture of HR and HP banks (eg. Kintex-7), and all HR banks (eg. Virtex-7).

To get 40 or more GPIO, you will probably need a board with a high-density FMC connector.  You can use a cable and the breakout board, XM105, to get convenient access to the pins of the FMC connector.

So, putting this all together, you could probably use a board with a Virtex-7 that has FMC connectors - for example the Xilinx VC707.

Cheers,
Mark

 

0 Kudos
bruce_karaffa
Scholar
Scholar
424 Views
Registered: ‎06-21-2017

A Virtex board may be a little pricey.  The Artix AC701 has an FMC connector and it is possible to set the IO voltage to 1.8V.  Judging by some posts on the forum, setting the voltage can be tricky.  I did it once, years ago. Just be careful.

0 Kudos