09-03-2012 06:59 AM
I have the following architecture:
SysTop.v => not edtitable
Engine.v => editable
LLRAM.v => editable
SysTop.v instanitates a PLL that outputs a clock "usr_clk". The "usr_clk" clock is port mapped to Engine.v and LLRAM.v inside the SysTop.v which is not editable. The frequency of the usr_clk is 200Mhz. The LLRAM operates at 200MHz.
I have components in the Engine.v that needs to operate at 100MHz so, I need to instantiate a PLL that recieves the input usr_clk and generates a 100 MHz. I can not place the PLL in the SysTop.v as it's not editable. Alternatively i will instantiate the PLL inside the Engine.v. But the problem now is that the usr_clk feeds a PLL in the Engine.v and feeds the LLRAM in the non-editable SysTop.v !!!! How can i solve such situation ? I recieve an error regarding the clock net saying that it has a multiple driver.
200MHz --------> LLRAM
--------> Engine/PLL -----> 100MHz
09-03-2012 06:25 PM
Can you post the exact error you're getting for the miltiple driver?
Also do you really need to have a 100 MHz clock or could you live
with a clock enable and use the 200 MHz clock for everything?
Finally what do you mean that SysTop.v is "not editable?" My understanding of
Verilog sources is that you can change them. Is this an encrypted source that can't
be touched? The ideal solution would seem to be to use the original PLL to generate
both 200 MHz and 100 MHz clocks.
09-13-2012 02:11 AM
I can use the clock enable but i did not try it before
I prepared the RTL and the CE generator. I need to know two things
How to apply the multicycle constraint ...
How will the tool fix the Skew on the CE net ? Is there a certain constraint i should apply ?
thanks in advance
09-13-2012 06:04 AM
The multicycle constraint will look something like:
NET "CE" TNM_NET = "F100MHz" ;
TIMESPEC TS_F100MHz = FROM : "F100MHz" : TO : "F100MHz" : 10 ns;
This assumes the name of the clock enable net is CE. Take note that the way the tools
propagate the signal to generate a group is that they follow the CE net to any flip-flop
and include such flops in the group. Thus is you generated the CE itself with a loop like:
always @ (posedge clk200) CE <= !CE;
then the CE signal itself will be in the timing group, which is bad. CE needs to meet the
tougher 200 MHz period constraint.
I usually work around this problem by creating a delay like:
always @ (posedge clk200 or posedge rst200)
CE <= 1'b0;
pre_CE <= 1'b0;
pre_CE <= !pre_CE;
CE <= pre_CE;
By default the tools will make sure that all signals
crossing from the 200 MHz group to the 100 MHz group meet the 5 ns period constraint
so there should be no issues with the CE net (assuming the build meets timing). If
CE is expected to have very high fanout you may need to replicate it to meet timing. If
that is the case, then make sure all duplicates of the CE signal are included in the
F100MHz time group declaration.