08-28-2012 04:44 AM
I have a Partial reconfiguration design in the FPGA (ISE14) that contain a block of BRAM memories generated by the coregen. I need to be able to change the content of these memories after the whole design is routed.
I know that similar task can be accomplished by the data2mem program. But to use data2mem I need to know which address in which BLOCKRAM corresponds to which address in the whole block of memories. For example, I have memory that has 6000 lines when every line store 8bit number and coregen uses 4 BlockRAM to implement such memory. Now, after the place and route, I have the file containing the number of line and the number to be stored in the memory (may be in coe) and I need to place these values into right blockram without running the place and route again.
Is there any way how to generate correct bmm file and connect it with the bitstream? Thanks you for every pointers.
08-28-2012 08:35 AM
This is all complicated by the fact that the address pins usually get swapped around for routability and so the RAM contents are scrambled. I'm not aware of anyone doing this successfully.
08-30-2012 03:31 AM
Actually I was under the impression that the XPS/SDK does similar think when it allows you to download the program for the microblaze after the bitstream was generated. I mean that in the XPS/SDK, I can generate HW design containing one or more microblaze processors and generate bitstream for this design. After that I may export the design into the SDK and write the program for microblaze (for example bootloader, or simple memory test) and then I can run this program in the FPGA without the need for rerouting.
Is there any possibility how to adopt the XPS/SDK approach to my own design?