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Visitor
Visitor
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Registered: ‎09-23-2019

ChipScope and Mapping

I have a current build that runs through implementation with no problem. However, when I add a chipscope core to the component, Xilinx ISE no longer combines the BlockRAM and FIFO cores into the same sites. Does anybody know what could be causing this?

Prior to adding chipscope component:

  • Number using BlockRAM only: 35
  • Number using FIFO only: 55
  • Number using BlockRAM and FIFO: 38
  • Total primitives used:
    • Number of 36k BlockRAM used: 12
    • Number of 18k BlockRAM used: 66
    • Number of 36k FIFO used: 17
    • Number of 18k FIFO used: 77

After adding chipscope component:

  • Number using BlockRAM only: 86
  • Number using FIFO only: 94
  • Total primitives used:
    • Number of 36k BlockRAM used: 20
    • Number of 18k BlockRAM used: 66
    • Number of 36k FIFO used: 17
    • Number of 18k FIFO used: 77

FPGA - Xilinx Virtex 5 - xc5vlx220t-2ff1738

Synthesis is being done with Synplify 2012.09. Map & P&R are done with Xilinx ISE 14.3

 

Update: This is not limited to adding chipscope apparently. I believe the decision to place RAM/FIFOS and whether or not to a single site for 2 of them is decided in the Xilinx ISE mapper. Am I incorrect here?

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Moderator
Moderator
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Registered: ‎01-16-2013

@jkelleher 

 

Can you check how the FIFO and BRAM cells placed from FPGA editor after PnR?

 

--Syed

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