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Visitor kanads
Visitor
5,862 Views
Registered: ‎07-29-2013

Chipscope core disappears after implementation

Hi, I am using Xilinx tools to synthesize and implement a modified OpenSPARCT1 on the XC5VLX110T. I am trying to debug the design using Chipscope coregen design flow. I am not using the core inserter flow since the debug signals I am trying to use disappear after synthesis. Now the problem I face is that after implementation, the Chipscope cores disappear (I confirm using the FPGA editor). I can see the debug signals connecting to the core in the synthesized netlist. The log isn't very helpful, but they do indicate that the chipscope ngc files are found during implementation. Has anyone had similar experience with Chipscope? Any help or pointers would be really appreciated. Let me know if I need to provide any more information. Thanks. PS. Due to compatibility issues, I am using ISE version 11.
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7 Replies
Xilinx Employee
Xilinx Employee
5,854 Views
Registered: ‎07-23-2012

Re: Chipscope core disappears after implementation

Hi,

When you state that the signals of your interest disappear after synthesis, does it mean that the tool is optimizing them? If yes, please verify your code and make sure that those signals are neither sourceless nor loadless.

Please see the "removed logic" section of mrp report. This gives the list of logic that is optimized by the tool and why.

I suspect that the optimization of the chipscope logic is the reason why you were unable to see the signal is FED.

Regards,
Krishna
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Visitor kanads
Visitor
5,852 Views
Registered: ‎07-29-2013

Re: Chipscope core disappears after implementation

Thanks for your reply. Yes, generally the debug signals are loadless during synthesis since I specifically meant to connect them to chipscope after synthesis in accordance to the core-inserter workflow. That is why I opted for the core-generator workflow and added the cores and connections in the source itself (it's also a little more convenient). I do not understand why they disappear after implementation though. The logs say nothing. Is there any way to figure out when, where and why during implementation the chipscope cores disappear? Note that in this workflow, chipscope cores are black-boxes during synthesis; I only specify the relevant ngc files during implementation.
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Community Manager
Community Manager
5,839 Views
Registered: ‎06-14-2012

Re: Chipscope core disappears after implementation

Unless a signal is an output of a register or other device primitives, it might not show up in the ChipScope inserter due to optimization performed by XST. This also applies to unused ports on the core that might not be hooked up in the design, but are needed for debug purposes.

 

Verilog

To preserve a net, Verilog uses the "keep" constraint.

Example for an output port:

(*keep= "true"*)
output [PCI_EXP_CFG_CAP_WIDTH-1 : 0] cfg_lstatus,

Example for a wire:

(*keep= "true"*)
wire trn_tdst_rdy;

VHDL

Use the KEEP constraint in VHDL as well.

For a core output port that needs to be preserved add the following before the end keyword:

(....
sys_clk : in std_logic;
sys_reset_n : in std_logic
);
attribute keep : string; -- this only needs to be added once
attribute keep of cfg_lstatus : signal is "true";
end v6_pcie_v1_4;

For any signal:

attribute keep : string; -- this only needs to be added once
attribute keep of trn_tdst_rdy_n: signal is "true";

 

 

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Visitor kanads
Visitor
5,822 Views
Registered: ‎07-29-2013

Re: Chipscope core disappears after implementation

Thanks a lot for your replies. Yes, I am aware of the keep attribute and have tried it; but they didn't work out as expected. I am however more interested in the core-generator work flow, where I modify the source code itself to include the Chipscope cores. Would you have any idea why the cores don't appear after implementation? Is there any way I could go about debugging this? The logs aren't helpful.
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Community Manager
Community Manager
5,793 Views
Registered: ‎06-14-2012

Re: Chipscope core disappears after implementation

Do you get the following error message?

"INFO: Found 0 Core Units in the JTAG device Chain"

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Visitor kanads
Visitor
5,783 Views
Registered: ‎07-29-2013

Re: Chipscope core disappears after implementation

Yes. The implementation completes without errors and when I try to monitor the board with Chipscope, I get this message. I can also check that the Chipscope ILA core is absent in the final implementation by using the fpga_editor.

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Community Manager
Community Manager
5,771 Views
Registered: ‎06-14-2012

Re: Chipscope core disappears after implementation

Can you check this? This collates for all aspects for missing cores.

 

http://www.xilinx.com/support/answers/19337.htm

 

http://www.xilinx.com/support/answers/42827.htm

 

Regards

Sikta

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