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Adventurer
Adventurer
339 Views
Registered: ‎11-18-2017

Conflict in I/O Standard on KCU116 evaluation kit (XCKU5P FPGA chip)

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Hello.

I'm using VIVADO and KCU116 evaluation kit (which contains Kintex UltraScale+ chip, xcku5p-ffvb676-2-e)

In the KCU116 Evaluation Board User Guide (UG1239) p29, it is indicated that

G12 Pin in the FPGA is connected to CLK_125MHZ_p and the I/O standard is LVDS (as mentioned in below figure).

  CLK.JPG

 

However, in the VIVADO, when I set the I/O standard to LVDS, an error occurs like below figure.

 

LVDS.png

 

From the KCU116 Evaluation Board User Guide (UG1239) p 29 G12 pin should be configured to LVDS I/O standard but in VIVADO, 

G12 pin can't use the LVDS I/O standard as illustrated above. The 2 cases are conflicting.

Why is this happening?

Thanks for your help.

 

ps. When I changed the LVDS to LVDS_25, the error disappears. Should I use LVDS_25 instead?

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Xilinx Employee
Xilinx Employee
309 Views
Registered: ‎05-08-2012

Re: Conflict in I/O Standard on KCU116 evaluation kit (XCKU5P FPGA chip)

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Hi @kimjaewon 

To find more information on the conflict, there are a couple things that you can do.

1. Hover the mouse over the red LVDS to see if there is a specific message. Normally there are for I/O incompatabilities.

2. manually set the constraint "set_property IOSTANDARD LVDS [get_ports <>]", and then report_drc after updating. This should give a message relating the port in question.

3. The information regarding LVDS within the SelectIO Guide would normally clarify the issue as well.

http://www.xilinx.com/support/documentation/user_guides/ug571-ultrascale-selectio.pdf#page=126


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1 Reply
Xilinx Employee
Xilinx Employee
310 Views
Registered: ‎05-08-2012

Re: Conflict in I/O Standard on KCU116 evaluation kit (XCKU5P FPGA chip)

Jump to solution

Hi @kimjaewon 

To find more information on the conflict, there are a couple things that you can do.

1. Hover the mouse over the red LVDS to see if there is a specific message. Normally there are for I/O incompatabilities.

2. manually set the constraint "set_property IOSTANDARD LVDS [get_ports <>]", and then report_drc after updating. This should give a message relating the port in question.

3. The information regarding LVDS within the SelectIO Guide would normally clarify the issue as well.

http://www.xilinx.com/support/documentation/user_guides/ug571-ultrascale-selectio.pdf#page=126


-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

 

 

---------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
---------------------------------------------------------------------------------------------

View solution in original post