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Observer
Observer
10,366 Views
Registered: ‎05-06-2014

Could not set property LOCK_PINS on instance DRPWE_LUT1B

Dear all:

 

I have use Vivado to generate a GTZ transceiver, and synthesis it , but in implimetation , there is an Error:

 

ERROR: [Vivado 12-3346] Could not set property 'LOCK_PINS' on instance gtwizard_0_i/inst/octal0_gtwizard_0_i/gtze2_inf_north/DRPWE_LUT1B. The cell is placed at site SLICE_X270Y260. The cell already has a 'LOCK_PINS' property. Please unplace the cell and reset the property prior to applying a new value. [/home/syshen/project_6/project_6.srcs/sources_1/ip/gtwizard_0/tcl/v7ht.tcl:9296]

 

What should I do?

 

Shen

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Xilinx Employee
Xilinx Employee
10,362 Views
Registered: ‎09-20-2012

Hi,

 

Are you running GTZ example design? If yes, the below is applicable.

 

Before opt_design step, the v7ht.tcl is sourced twice. The LOCK_PINS contained in v7ht.tcl being executed twice is the root cause for the error message. 
Since the LOCK_PINS property is set correctly, the error message can be ignored safely.

 

The reading v7ht.tcl twice issue is fixed in Vivado 2014.2.

 

Thanks,

Deepika.

Thanks,
Deepika.
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Xilinx Employee
Xilinx Employee
10,347 Views
Registered: ‎08-01-2012

If that is the case (If you are running GTZ example design in Virtex-7H)

It's not Vivado's bug. 
%read_checkpoint command will read the XDC in the same dir simultaneously, which causes XDC is read twice.
The workaround is to move the XDC file to the dir different from DCP file's.

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Observer
Observer
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Registered: ‎05-06-2014

has 2014.2 released?
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Xilinx Employee
Xilinx Employee
10,333 Views
Registered: ‎09-20-2012

No, not yet.  It will be in month of June (tentative).

 

Is the error stopping you from moving further with bitstream generation?

 

Thanks.

Thanks,
Deepika.
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Observer
Observer
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Registered: ‎05-06-2014

But if I move it away, how should I be found by vivado?

 

Shen

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Observer
Observer
10,328 Views
Registered: ‎05-06-2014

I means , if I move the XDC file to the dir different from DCP file', just as suggested by Kodali, how can I make vivado to find it?

Shen
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Xilinx Employee
Xilinx Employee
10,318 Views
Registered: ‎09-20-2012

Hi Shen,

 

I dont think moving the XDC will help here.

 

 

As I mentioned earlier you can ignore this error. Are you not able to proceed to bitstream generation because of this error?

 

Thanks,

Deepika.

Thanks,
Deepika.
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Observer
Observer
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Registered: ‎05-06-2014

I can proceed , but other errors or critical warning pop up:

 

CRITICAL WARNING: [Place 30-664] Unable to find any site for BUFG instance clkf_buf_tx which is connected to terminal "TXUSRCLK1" of the GTZ instance placed on site GTZE2_OCTAL_X0Y0. This may lead to issues with placement later in the flow.

 

 

I have create an BUFG, and use TXCORECLK of the generated GTZ to drive this BUFG's I pin,

and then use this BUFG's O pin to drive TXUSRCLK1 pin of the above generated GTZ instance at GTZE2_OCTAL_X0Y0, so what is the problem with this?

 

I want to attach my log, but this message always fail to be post, so I have no choice but past it below 

 


*** Running vivado
with args -log chip.vdi -applog -m64 -messageDb vivado.pb -mode batch -source chip.tcl -notrace


****** Vivado v2014.1 (64-bit)
**** SW Build 881834 on Fri Apr 4 13:56:21 MDT 2014
**** IP Build 877625 on Fri Mar 28 16:29:15 MDT 2014
** Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.

source chip.tcl -notrace
Design is defaulting to srcset: sources_1
Design is defaulting to constrset: constrs_1
INFO: [Project 1-454] Reading design checkpoint '/home/syshen/project_6/project_6.runs/clk_wiz_0_synth_1/clk_wiz_0.dcp' for cell 'inst_pll'
INFO: [Project 1-454] Reading design checkpoint '/home/syshen/project_6/project_6.runs/gtwizard_0_synth_1/gtwizard_0.dcp' for cell 'gtwizard_0_i'
INFO: [Netlist 29-17] Analyzing 2 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2014.1
INFO: [Device 21-44] Node exclude file processed
Loading clock regions from /home/syshen/Xilinx/Vivado/2014.1/data/parts/xilinx/virtex7/virtex7/xc7vh580t/ClockRegion.xml
Loading clock buffers from /home/syshen/Xilinx/Vivado/2014.1/data/parts/xilinx/virtex7/virtex7/xc7vh580t/ClockBuffers.xml
Loading clock placement rules from /home/syshen/Xilinx/Vivado/2014.1/data/parts/xilinx/virtex7/ClockPlacerRules.xml
Loading package pin functions from /home/syshen/Xilinx/Vivado/2014.1/data/parts/xilinx/virtex7/PinFunctions.xml...
Loading package from /home/syshen/Xilinx/Vivado/2014.1/data/parts/xilinx/virtex7/virtex7/xc7vh580t/hcg1155/Package.xml
Loading io standards from /home/syshen/Xilinx/Vivado/2014.1/data/./parts/xilinx/virtex7/IOStandards.xml
Loading device configuration modes from /home/syshen/Xilinx/Vivado/2014.1/data/parts/xilinx/virtex7/ConfigModes.xml
INFO: [Opt 31-140] Inserted 11 IBUFs to IO ports without IO buffers.
INFO: [Opt 31-141] Inserted 8 OBUFs to IO ports without IO buffers.
Parsing XDC File [/home/syshen/project_6/project_6.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc] for cell 'inst_pll/inst'
INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/syshen/project_6/project_6.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc:56]
INFO: [Timing 38-2] Deriving generated clocks [/home/syshen/project_6/project_6.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc:56]
get_clocks: Time (s): cpu = 00:00:23 ; elapsed = 00:00:23 . Memory (MB): peak = 1827.277 ; gain = 458.637
Finished Parsing XDC File [/home/syshen/project_6/project_6.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc] for cell 'inst_pll/inst'
Parsing XDC File [/home/syshen/project_6/project_6.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc] for cell 'inst_pll/inst'
Finished Parsing XDC File [/home/syshen/project_6/project_6.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc] for cell 'inst_pll/inst'
Parsing XDC File [/home/syshen/project_6/project_6.srcs/constrs_1/imports/new/chip.xdc]
Finished Parsing XDC File [/home/syshen/project_6/project_6.srcs/constrs_1/imports/new/chip.xdc]
INFO: [Project 1-538] Ignoring constraints in dcp '/home/syshen/project_6/project_6.runs/clk_wiz_0_synth_1/clk_wiz_0.dcp'
INFO: [Project 1-538] Ignoring constraints in dcp '/home/syshen/project_6/project_6.runs/gtwizard_0_synth_1/gtwizard_0.dcp'
INFO: [Opt 31-138] Pushed 0 inverter(s).
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.

link_design: Time (s): cpu = 00:00:46 ; elapsed = 00:00:47 . Memory (MB): peak = 1827.277 ; gain = 1000.137
Sourcing Tcl File [/home/syshen/project_6/project_6.srcs/sources_1/ip/gtwizard_0/tcl/v7ht.tcl]
Finished Sourcing Tcl File [/home/syshen/project_6/project_6.srcs/sources_1/ip/gtwizard_0/tcl/v7ht.tcl]
read_xdc: Time (s): cpu = 00:01:10 ; elapsed = 00:01:11 . Memory (MB): peak = 1871.949 ; gain = 44.672
Sourcing Tcl File [/home/syshen/project_6/project_6.srcs/sources_1/ip/gtwizard_0/tcl/v7ht.tcl]
ERROR: [Vivado 12-3346] Could not set property 'LOCK_PINS' on instance gtwizard_0_i/inst/octal0_gtwizard_0_i/gtze2_inf_north/DRPWE_LUT1B. The cell is placed at site SLICE_X270Y260. The cell already has a 'LOCK_PINS' property. Please unplace the cell and reset the property prior to applying a new value. [/home/syshen/project_6/project_6.srcs/sources_1/ip/gtwizard_0/tcl/v7ht.tcl:9296]
Finished Sourcing Tcl File [/home/syshen/project_6/project_6.srcs/sources_1/ip/gtwizard_0/tcl/v7ht.tcl]
INFO: [Designutils 20-663] Invalid constraints found, use command 'write_xdc -constraints invalid <file>' to save all the invalid constraints to a file
read_xdc: Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 1876.605 ; gain = 4.656
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7vh580t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vh580t'
Running DRC as a precondition to command opt_design

Starting DRC Task
INFO: [Drc 23-27] Running DRC with 8 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.

Time (s): cpu = 00:00:00.29 ; elapsed = 00:00:00.28 . Memory (MB): peak = 1906.750 ; gain = 4.957

Starting Logic Optimization Task

Phase 1 Retarget

INFO: [Opt 31-138] Pushed 0 inverter(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 1 Retarget | Checksum: 134976e98

Time (s): cpu = 00:00:00.33 ; elapsed = 00:00:00.33 . Memory (MB): peak = 1906.750 ; gain = 0.000

Phase 2 Constant Propagation
INFO: [Opt 31-138] Pushed 0 inverter(s).
INFO: [Opt 31-10] Eliminated 170 cells.
Phase 2 Constant Propagation | Checksum: 1750f6ed2

Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1906.750 ; gain = 0.000

Phase 3 Sweep
WARNING: [Opt 31-6] Deleting driverless net: gtwizard_0_i/oct0_gtrefclk1n_in.
WARNING: [Opt 31-6] Deleting driverless net: gtwizard_0_i/oct0_gtrefclk1p_in.
WARNING: [Opt 31-6] Deleting driverless net: gtwizard_0_i/oct0_rxlatclk_in.
WARNING: [Opt 31-6] Deleting driverless net: gtwizard_0_i/oct0_txlatclk_in.
WARNING: [Opt 31-6] Deleting driverless net: gtwizard_0_i/inst/oct0_gtrefclk1n_in.
WARNING: [Opt 31-6] Deleting driverless net: gtwizard_0_i/inst/oct0_gtrefclk1p_in.
WARNING: [Opt 31-6] Deleting driverless net: gtwizard_0_i/inst/oct0_rxlatclk_in.
WARNING: [Opt 31-6] Deleting driverless net: gtwizard_0_i/inst/oct0_txlatclk_in.
WARNING: [Opt 31-6] Deleting driverless net: gtwizard_0_i/inst/octal0_gtwizard_0_i/oct0_gtrefclk1n_in.
WARNING: [Opt 31-6] Deleting driverless net: gtwizard_0_i/inst/octal0_gtwizard_0_i/oct0_gtrefclk1p_in.
WARNING: [Opt 31-6] Deleting driverless net: gtwizard_0_i/inst/octal0_gtwizard_0_i/oct0_rxlatclk_in.
WARNING: [Opt 31-6] Deleting driverless net: gtwizard_0_i/inst/octal0_gtwizard_0_i/oct0_txlatclk_in.
INFO: [Opt 31-12] Eliminated 158 unconnected nets.
INFO: [Opt 31-11] Eliminated 6 unconnected cells.
Phase 3 Sweep | Checksum: efe5118f

Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1906.750 ; gain = 0.000
Ending Logic Optimization Task | Checksum: efe5118f

Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 1906.750 ; gain = 0.000
Implement Debug Cores | Checksum: 134976e98
Logic Optimization | Checksum: 134976e98

Starting Power Optimization Task
Ending Power Optimization Task | Checksum: efe5118f

Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1906.750 ; gain = 0.000
INFO: [Common 17-83] Releasing license: Implementation
26 Infos, 12 Warnings, 0 Critical Warnings and 1 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 1906.750 ; gain = 30.141
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00.61 ; elapsed = 00:00:00.62 . Memory (MB): peak = 1906.754 ; gain = 0.000
Command: place_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7vh580t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vh580t'
Running DRC as a precondition to command place_design
INFO: [Drc 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.

Starting Placer Task
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs

Phase 1 Placer Initialization

Phase 1.1 Placer Initialization Core
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1906.812 ; gain = 0.000

Phase 1.1.1 Mandatory Logic Optimization
INFO: [Opt 31-140] Inserted 1 IBUFs to IO ports without IO buffers.
INFO: [Opt 31-141] Inserted 0 OBUFs to IO ports without IO buffers.
INFO: [Opt 31-138] Pushed 0 inverter(s).
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1906.812 ; gain = 0.000
Phase 1.1.1 Mandatory Logic Optimization | Checksum: 92a48beb

Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1906.812 ; gain = 0.000

Phase 1.1.2 Build Super Logic Region (SLR) Database
Phase 1.1.2 Build Super Logic Region (SLR) Database | Checksum: 92a48beb

Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1906.812 ; gain = 0.000

Phase 1.1.3 Add Constraints
Phase 1.1.3 Add Constraints | Checksum: 92a48beb

Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1906.812 ; gain = 0.000

Phase 1.1.4 Build Shapes/ HD Config

Phase 1.1.4.1 Build Macros
Phase 1.1.4.1 Build Macros | Checksum: bc30ee4b

Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1920.777 ; gain = 13.965
Phase 1.1.4 Build Shapes/ HD Config | Checksum: bc30ee4b

Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1920.777 ; gain = 13.965

Phase 1.1.5 IO Placement/ Clock Placement/ Build Placer Device

Phase 1.1.5.1 Pre-Place Cells
CRITICAL WARNING: [Place 30-664] Unable to find any site for BUFG instance clkf_buf_tx which is connected to terminal "TXUSRCLK1" of the GTZ instance placed on site GTZE2_OCTAL_X0Y0. This may lead to issues with placement later in the flow.
Phase 1.1.5.1 Pre-Place Cells | Checksum: 767ab0fb

Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1920.777 ; gain = 13.965

Phase 1.1.5.2 Implementation Feasibility check
Phase 1.1.5.2 Implementation Feasibility check | Checksum: 767ab0fb

Time (s): cpu = 00:00:10 ; elapsed = 00:00:08 . Memory (MB): peak = 1920.777 ; gain = 13.965
INFO: [Timing 38-35] Done setting XDC timing constraints.

Phase 1.1.5.3 Implementation Feasibility check On IDelay
Phase 1.1.5.3 Implementation Feasibility check On IDelay | Checksum: 767ab0fb

Time (s): cpu = 00:00:15 ; elapsed = 00:00:12 . Memory (MB): peak = 1931.035 ; gain = 24.223
Phase 1.1.5 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 7451ebb8

Time (s): cpu = 00:00:15 ; elapsed = 00:00:12 . Memory (MB): peak = 1931.035 ; gain = 24.223

Phase 1.1.6 Build Placer Netlist Model

Phase 1.1.6.1 Place Init Design

Phase 1.1.6.1.1 Build Clock Data
Phase 1.1.6.1.1 Build Clock Data | Checksum: 10c6e2090

Time (s): cpu = 00:00:22 ; elapsed = 00:00:15 . Memory (MB): peak = 1963.535 ; gain = 56.723
Phase 1.1.6.1 Place Init Design | Checksum: c3590e36

Time (s): cpu = 00:00:23 ; elapsed = 00:00:15 . Memory (MB): peak = 1963.535 ; gain = 56.723
Phase 1.1.6 Build Placer Netlist Model | Checksum: c3590e36

Time (s): cpu = 00:00:23 ; elapsed = 00:00:15 . Memory (MB): peak = 1963.535 ; gain = 56.723

Phase 1.1.7 Constrain Clocks/Macros

Phase 1.1.7.1 Constrain Global/Regional Clocks
Phase 1.1.7.1 Constrain Global/Regional Clocks | Checksum: c3590e36

Time (s): cpu = 00:00:23 ; elapsed = 00:00:15 . Memory (MB): peak = 1963.535 ; gain = 56.723
Phase 1.1.7 Constrain Clocks/Macros | Checksum: c3590e36

Time (s): cpu = 00:00:23 ; elapsed = 00:00:16 . Memory (MB): peak = 1963.535 ; gain = 56.723
Phase 1.1 Placer Initialization Core | Checksum: c3590e36

Time (s): cpu = 00:00:23 ; elapsed = 00:00:16 . Memory (MB): peak = 1963.535 ; gain = 56.723
Phase 1 Placer Initialization | Checksum: c3590e36

Time (s): cpu = 00:00:23 ; elapsed = 00:00:16 . Memory (MB): peak = 1963.535 ; gain = 56.723

Phase 2 Global Placement

Phase 2.1 Run Budgeter
Phase 2.1 Run Budgeter | Checksum: f61f2f86

Time (s): cpu = 00:00:35 ; elapsed = 00:00:25 . Memory (MB): peak = 1982.645 ; gain = 75.832
Phase 2 Global Placement | Checksum: 18babe728

Time (s): cpu = 00:00:54 ; elapsed = 00:00:31 . Memory (MB): peak = 2016.895 ; gain = 110.082

Phase 3 Detail Placement

Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: 18babe728

Time (s): cpu = 00:00:54 ; elapsed = 00:00:31 . Memory (MB): peak = 2016.895 ; gain = 110.082

Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 173ba5cc0

Time (s): cpu = 00:00:57 ; elapsed = 00:00:33 . Memory (MB): peak = 2021.113 ; gain = 114.301

Phase 3.3 Area Swap Optimization
Phase 3.3 Area Swap Optimization | Checksum: 1c0d5299d

Time (s): cpu = 00:00:57 ; elapsed = 00:00:33 . Memory (MB): peak = 2022.363 ; gain = 115.551

Phase 3.4 Timing Path Optimizer
Phase 3.4 Timing Path Optimizer | Checksum: 1d23f269e

Time (s): cpu = 00:00:58 ; elapsed = 00:00:34 . Memory (MB): peak = 2022.363 ; gain = 115.551

Phase 3.5 Commit Small Macros & Core Logic
Phase 3.5 Commit Small Macros & Core Logic | Checksum: 1bd455eda

Time (s): cpu = 00:01:04 ; elapsed = 00:00:40 . Memory (MB): peak = 2082.609 ; gain = 175.797

Phase 3.6 Re-assign LUT pins
Phase 3.6 Re-assign LUT pins | Checksum: 1bd455eda

Time (s): cpu = 00:01:05 ; elapsed = 00:00:40 . Memory (MB): peak = 2082.609 ; gain = 175.797
Phase 3 Detail Placement | Checksum: 1bd455eda

Time (s): cpu = 00:01:06 ; elapsed = 00:00:41 . Memory (MB): peak = 2082.609 ; gain = 175.797

Phase 4 Post Placement Optimization and Clean-Up

Phase 4.1 PCOPT Shape updates
Phase 4.1 PCOPT Shape updates | Checksum: 1e6e492b4

Time (s): cpu = 00:01:06 ; elapsed = 00:00:41 . Memory (MB): peak = 2082.609 ; gain = 175.797

Phase 4.2 Post Placement Optimization

Phase 4.2.1 Post Placement Timing Optimization
INFO: [Place 30-746] Post Placement Timing Summary WNS=36.846. For the most accurate timing information please run report_timing.
Phase 4.2.1 Post Placement Timing Optimization | Checksum: 2ad2567ac

Time (s): cpu = 00:01:11 ; elapsed = 00:00:43 . Memory (MB): peak = 2082.609 ; gain = 175.797
Phase 4.2 Post Placement Optimization | Checksum: 2ad2567ac

Time (s): cpu = 00:01:12 ; elapsed = 00:00:43 . Memory (MB): peak = 2082.609 ; gain = 175.797

Phase 4.3 Post Placement Cleanup
Phase 4.3 Post Placement Cleanup | Checksum: 2ad2567ac

Time (s): cpu = 00:01:12 ; elapsed = 00:00:43 . Memory (MB): peak = 2082.609 ; gain = 175.797

Phase 4.4 Placer Reporting

Phase 4.4.1 Restore STA
Phase 4.4.1 Restore STA | Checksum: 2ad2567ac

Time (s): cpu = 00:01:12 ; elapsed = 00:00:43 . Memory (MB): peak = 2082.609 ; gain = 175.797
Phase 4.4 Placer Reporting | Checksum: 2ad2567ac

Time (s): cpu = 00:01:12 ; elapsed = 00:00:43 . Memory (MB): peak = 2082.609 ; gain = 175.797

Phase 4.5 Final Placement Cleanup
Phase 4.5 Final Placement Cleanup | Checksum: 3133b9b4e

Time (s): cpu = 00:01:13 ; elapsed = 00:00:43 . Memory (MB): peak = 2082.609 ; gain = 175.797
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 3133b9b4e

Time (s): cpu = 00:01:13 ; elapsed = 00:00:44 . Memory (MB): peak = 2082.609 ; gain = 175.797
Ending Placer Task | Checksum: 223f91b4e

Time (s): cpu = 00:01:13 ; elapsed = 00:00:44 . Memory (MB): peak = 2082.609 ; gain = 175.797
INFO: [Common 17-83] Releasing license: Implementation
37 Infos, 12 Warnings, 1 Critical Warnings and 1 Errors encountered.
place_design completed successfully
place_design: Time (s): cpu = 00:01:30 ; elapsed = 00:01:01 . Memory (MB): peak = 2082.609 ; gain = 175.855
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2082.613 ; gain = 0.000
report_utilization: Time (s): cpu = 00:00:00.52 ; elapsed = 00:00:00.59 . Memory (MB): peak = 2082.613 ; gain = 0.000
Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7vh580t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vh580t'
Running DRC as a precondition to command route_design
INFO: [Drc 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.


Starting Routing Task
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs

Starting Route Task

Phase 1 Build RT Design
Phase 1 Build RT Design | Checksum: 105ef8a3e

Time (s): cpu = 00:02:37 ; elapsed = 00:02:00 . Memory (MB): peak = 2568.617 ; gain = 403.562

Phase 2 Router Initialization

Phase 2.1 Create Timer
Phase 2.1 Create Timer | Checksum: 105ef8a3e

Time (s): cpu = 00:02:38 ; elapsed = 00:02:00 . Memory (MB): peak = 2568.621 ; gain = 403.566
Number of Nodes with overlaps = 0

Phase 2.2 Update Timing
Phase 2.2 Update Timing | Checksum: 11c142414

Time (s): cpu = 00:03:02 ; elapsed = 00:02:18 . Memory (MB): peak = 2831.031 ; gain = 665.977
INFO: [Route 35-57] Estimated Timing Summary | WNS=-2.15e+06| TNS=-8.16e+07| WHS=-0.136 | THS=-1.35 |

Phase 2 Router Initialization | Checksum: 11c142414

Time (s): cpu = 00:03:04 ; elapsed = 00:02:19 . Memory (MB): peak = 2831.031 ; gain = 665.977

Phase 3 Initial Routing

Phase 3.1 Initial Routing Verification

Post Initial-Routing Verification
---------------------------------
CRITICAL WARNING: [Route 35-54] Net: inst_pll/inst/clk_out1 is not completely routed.
Resolution: Run report_route_status for more information.
CRITICAL WARNING: [Route 35-54] Net: clkpma_tx_BUFG is not completely routed.
Resolution: Run report_route_status for more information.

Unroutable connection Types:
----------------------------
Type 1 : BUFGCTRL.O->GTZE2_OCTAL.DRPCLK1
-----Num Open nets: 1
-----Representative Net: Net[1] inst_pll/inst/clk_out1
-----BUFGCTRL_X0Y14.O -> GTZE2_OCTAL_X0Y0.DRPCLK1
-----Driver Term: inst_pll/inst/clkout1_buf/O Load Term [8]: gtwizard_0_i/inst/octal0_gtwizard_0_i/gtze2_octal_north/DRPCLK1
Type 2 : BUFGCTRL.O->GTZE2_OCTAL.TXUSRCLK1
-----Num Open nets: 1
-----Representative Net: Net[13] clkpma_tx_BUFG
-----BUFGCTRL_X0Y63.O -> GTZE2_OCTAL_X0Y0.TXUSRCLK1
-----Driver Term: clkf_buf_tx/O Load Term [1377]: gtwizard_0_i/inst/octal0_gtwizard_0_i/gtze2_octal_north/TXUSRCLK1
Type 3 : BUFGCTRL.O->GTZE2_OCTAL.TXUSRCLK2
-----Num Open nets: 1
-----Representative Net: Net[13] clkpma_tx_BUFG
-----BUFGCTRL_X0Y63.O -> GTZE2_OCTAL_X0Y0.TXUSRCLK2
-----Driver Term: clkf_buf_tx/O Load Term [1378]: gtwizard_0_i/inst/octal0_gtwizard_0_i/gtze2_octal_north/TXUSRCLK2
Type 4 : BUFGCTRL.O->GTZE2_OCTAL.TXUSRCLK3
-----Num Open nets: 1
-----Representative Net: Net[13] clkpma_tx_BUFG
-----BUFGCTRL_X0Y63.O -> GTZE2_OCTAL_X0Y0.TXUSRCLK3
-----Driver Term: clkf_buf_tx/O Load Term [1379]: gtwizard_0_i/inst/octal0_gtwizard_0_i/gtze2_octal_north/TXUSRCLK3
Type 5 : BUFGCTRL.O->GTZE2_OCTAL.TXUSRCLK4
-----Num Open nets: 1
-----Representative Net: Net[13] clkpma_tx_BUFG
-----BUFGCTRL_X0Y63.O -> GTZE2_OCTAL_X0Y0.TXUSRCLK4
-----Driver Term: clkf_buf_tx/O Load Term [1380]: gtwizard_0_i/inst/octal0_gtwizard_0_i/gtze2_octal_north/TXUSRCLK4
Type 6 : BUFGCTRL.O->GTZE2_OCTAL.TXUSRCLK5
-----Num Open nets: 1
-----Representative Net: Net[13] clkpma_tx_BUFG
-----BUFGCTRL_X0Y63.O -> GTZE2_OCTAL_X0Y0.TXUSRCLK5
-----Driver Term: clkf_buf_tx/O Load Term [1381]: gtwizard_0_i/inst/octal0_gtwizard_0_i/gtze2_octal_north/TXUSRCLK5
Type 7 : BUFGCTRL.O->GTZE2_OCTAL.TXUSRCLK6
-----Num Open nets: 1
-----Representative Net: Net[13] clkpma_tx_BUFG
-----BUFGCTRL_X0Y63.O -> GTZE2_OCTAL_X0Y0.TXUSRCLK6
-----Driver Term: clkf_buf_tx/O Load Term [1382]: gtwizard_0_i/inst/octal0_gtwizard_0_i/gtze2_octal_north/TXUSRCLK6
Type 8 : BUFGCTRL.O->GTZE2_OCTAL.TXUSRCLK7
-----Num Open nets: 1
-----Representative Net: Net[13] clkpma_tx_BUFG
-----BUFGCTRL_X0Y63.O -> GTZE2_OCTAL_X0Y0.TXUSRCLK7
-----Driver Term: clkf_buf_tx/O Load Term [1383]: gtwizard_0_i/inst/octal0_gtwizard_0_i/gtze2_octal_north/TXUSRCLK7
Phase 3.1 Initial Routing Verification | Checksum: 143a445bc

Time (s): cpu = 00:03:25 ; elapsed = 00:02:29 . Memory (MB): peak = 3329.031 ; gain = 1163.977
Phase 3 Initial Routing | Checksum: 143a445bc

Time (s): cpu = 00:03:25 ; elapsed = 00:02:29 . Memory (MB): peak = 3329.031 ; gain = 1163.977

Phase 4 Rip-up And Reroute

Phase 4.1 Global Iteration 0
Number of Nodes with overlaps = 1375
Number of Nodes with overlaps = 1
Number of Nodes with overlaps = 0

Phase 4.1.1 Update Timing
Phase 4.1.1 Update Timing | Checksum: 12845a06d

Time (s): cpu = 00:03:33 ; elapsed = 00:02:32 . Memory (MB): peak = 3329.031 ; gain = 1163.977
INFO: [Route 35-57] Estimated Timing Summary | WNS=-2.15e+06| TNS=-8.16e+07| WHS=N/A | THS=N/A |


Phase 4.1.2 GlobIterForTiming

Phase 4.1.2.1 Update Timing
Phase 4.1.2.1 Update Timing | Checksum: 12845a06d

Time (s): cpu = 00:03:34 ; elapsed = 00:02:32 . Memory (MB): peak = 3329.031 ; gain = 1163.977

Phase 4.1.2.2 Fast Budgeting
Phase 4.1.2.2 Fast Budgeting | Checksum: 12845a06d

Time (s): cpu = 00:03:34 ; elapsed = 00:02:32 . Memory (MB): peak = 3329.031 ; gain = 1163.977
Phase 4.1.2 GlobIterForTiming | Checksum: 12845a06d

Time (s): cpu = 00:03:34 ; elapsed = 00:02:32 . Memory (MB): peak = 3329.031 ; gain = 1163.977
Phase 4.1 Global Iteration 0 | Checksum: 12845a06d

Time (s): cpu = 00:03:34 ; elapsed = 00:02:32 . Memory (MB): peak = 3329.031 ; gain = 1163.977
Phase 4 Rip-up And Reroute | Checksum: 12845a06d

Time (s): cpu = 00:03:34 ; elapsed = 00:02:32 . Memory (MB): peak = 3329.031 ; gain = 1163.977

Phase 5 Delay CleanUp

Phase 5.1 Update Timing
Phase 5.1 Update Timing | Checksum: 12845a06d

Time (s): cpu = 00:03:35 ; elapsed = 00:02:33 . Memory (MB): peak = 3329.031 ; gain = 1163.977
INFO: [Route 35-57] Estimated Timing Summary | WNS=-2.15e+06| TNS=-8.16e+07| WHS=N/A | THS=N/A |

Number of Nodes with overlaps = 0
Phase 5 Delay CleanUp | Checksum: 12845a06d

Time (s): cpu = 00:03:35 ; elapsed = 00:02:33 . Memory (MB): peak = 3329.031 ; gain = 1163.977

Phase 6 Clock Skew Optimization
Phase 6 Clock Skew Optimization | Checksum: 12845a06d

Time (s): cpu = 00:03:35 ; elapsed = 00:02:33 . Memory (MB): peak = 3329.031 ; gain = 1163.977

Phase 7 Post Hold Fix

Phase 7.1 Update Timing
Phase 7.1 Update Timing | Checksum: 12845a06d

Time (s): cpu = 00:03:36 ; elapsed = 00:02:33 . Memory (MB): peak = 3329.031 ; gain = 1163.977
INFO: [Route 35-57] Estimated Timing Summary | WNS=-2.15e+06| TNS=-8.16e+07| WHS=-2.15e+06| THS=-1.14e+08|

Phase 7 Post Hold Fix | Checksum: cbc4dcdf

Time (s): cpu = 00:03:36 ; elapsed = 00:02:33 . Memory (MB): peak = 3329.031 ; gain = 1163.977

Phase 8 Route finalize

Router Utilization Summary
Global Vertical Routing Utilization = 0.404696 %
Global Horizontal Routing Utilization = 0.396081 %
Routable Net Status*
*Does not include unroutable nets such as driverless and loadless.
Run report_route_status for detailed report.
Number of Failed Nets = 2
Number of Unrouted Nets = 0
Number of Partially Routed Nets = 2
Number of Node Overlaps = 0

Congestion Report
North Dir 1x1 Area, Max Cong = 55.8559%, No Congested Regions.
South Dir 1x1 Area, Max Cong = 49.5495%, No Congested Regions.
East Dir 1x1 Area, Max Cong = 61.7647%, No Congested Regions.
West Dir 1x1 Area, Max Cong = 52.9412%, No Congested Regions.
Phase 8 Route finalize | Checksum: cbc4dcdf

Time (s): cpu = 00:03:37 ; elapsed = 00:02:34 . Memory (MB): peak = 3329.031 ; gain = 1163.977

Phase 9 Verifying routed nets
CRITICAL WARNING: [Route 35-54] Net: inst_pll/inst/clk_out1 is not completely routed.
Resolution: Run report_route_status for more information.
CRITICAL WARNING: [Route 35-54] Net: clkpma_tx_BUFG is not completely routed.
Resolution: Run report_route_status for more information.
CRITICAL WARNING: [Route 35-7] Design has 4 unroutable pins, potentially caused by placement issues.
CRITICAL WARNING: [Route 35-8] Design has 4 unrouted pins, that are still reachable.

Verification failed
Phase 9 Verifying routed nets | Checksum: cbc4dcdf

Time (s): cpu = 00:05:43 ; elapsed = 00:04:39 . Memory (MB): peak = 3329.031 ; gain = 1163.977
CRITICAL WARNING: [Route 35-1] Design is not completely routed. There are 2 nets that are not completely routed.

Phase 10 Depositing Routes
Phase 10 Depositing Routes | Checksum: 168ced3ae

Time (s): cpu = 00:05:45 ; elapsed = 00:04:41 . Memory (MB): peak = 3329.031 ; gain = 1163.977

Phase 11 Post Router Timing

Phase 11.1 Update Timing
Phase 11.1 Update Timing | Checksum: 168ced3ae

Time (s): cpu = 00:05:45 ; elapsed = 00:04:41 . Memory (MB): peak = 3329.031 ; gain = 1163.977
INFO: [Route 35-57] Estimated Timing Summary | WNS=-2.15e+06| TNS=-8.16e+07| WHS=-2.15e+06| THS=-1.14e+08|

WARNING: [Route 35-328] Router estimated timing not met.
Resolution: For a complete and accurate timing signoff, report_timing_summary must be run after route_design. Alternatively, route_design can be run with the -timing_summary option to enable a complete timing signoff at the end of route_design.
Phase 11 Post Router Timing | Checksum: 168ced3ae

Time (s): cpu = 00:05:45 ; elapsed = 00:04:41 . Memory (MB): peak = 3329.031 ; gain = 1163.977
INFO: [Route 35-77] Router completed with failures. Please check the log file for Critical Warnings and run report_route_status for a summary of routing status.
Ending Route Task | Checksum: 168ced3ae

Time (s): cpu = 00:05:46 ; elapsed = 00:04:42 . Memory (MB): peak = 3329.031 ; gain = 1163.977

Routing Is Done.

Time (s): cpu = 00:05:46 ; elapsed = 00:04:42 . Memory (MB): peak = 3329.035 ; gain = 1163.980
INFO: [Common 17-83] Releasing license: Implementation
49 Infos, 13 Warnings, 8 Critical Warnings and 1 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:06:04 ; elapsed = 00:04:58 . Memory (MB): peak = 3329.035 ; gain = 1246.422
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 3329.035 ; gain = 0.000
INFO: [Drc 23-27] Running DRC with 8 threads
INFO: [Coretcl 2-168] The results of DRC are in file /home/syshen/project_6/project_6.runs/impl_2/chip_drc_routed.rpt.
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2G, Delay Type: min_max, Constraints type: SDC.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
Running Vector-less Activity Propagation...

Finished Running Vector-less Activity Propagation
report_power: Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 3329.035 ; gain = 0.000
INFO: [Common 17-206] Exiting Vivado at Thu May 8 23:18:05 2014...

*** Running vivado
with args -log chip.vdi -applog -m64 -messageDb vivado.pb -mode batch -source chip.tcl -notrace


****** Vivado v2014.1 (64-bit)
**** SW Build 881834 on Fri Apr 4 13:56:21 MDT 2014
**** IP Build 877625 on Fri Mar 28 16:29:15 MDT 2014
** Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.

source chip.tcl -notrace
Command: open_checkpoint chip_routed.dcp
INFO: [Netlist 29-17] Analyzing 14 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2014.1
INFO: [Device 21-44] Node exclude file processed
Loading clock regions from /home/syshen/Xilinx/Vivado/2014.1/data/parts/xilinx/virtex7/virtex7/xc7vh580t/ClockRegion.xml
Loading clock buffers from /home/syshen/Xilinx/Vivado/2014.1/data/parts/xilinx/virtex7/virtex7/xc7vh580t/ClockBuffers.xml
Loading clock placement rules from /home/syshen/Xilinx/Vivado/2014.1/data/parts/xilinx/virtex7/ClockPlacerRules.xml
Loading package pin functions from /home/syshen/Xilinx/Vivado/2014.1/data/parts/xilinx/virtex7/PinFunctions.xml...
Loading package from /home/syshen/Xilinx/Vivado/2014.1/data/parts/xilinx/virtex7/virtex7/xc7vh580t/hcg1155/Package.xml
Loading io standards from /home/syshen/Xilinx/Vivado/2014.1/data/./parts/xilinx/virtex7/IOStandards.xml
Loading device configuration modes from /home/syshen/Xilinx/Vivado/2014.1/data/parts/xilinx/virtex7/ConfigModes.xml
Parsing XDC File [/home/syshen/project_6/project_6.runs/impl_2/.Xil/Vivado-10925-svr641_7/dcp/chip_early.xdc]
INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/syshen/project_6/project_6.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc:56]
INFO: [Timing 38-2] Deriving generated clocks [/home/syshen/project_6/project_6.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc:56]
get_clocks: Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 1826.707 ; gain = 459.527
Finished Parsing XDC File [/home/syshen/project_6/project_6.runs/impl_2/.Xil/Vivado-10925-svr641_7/dcp/chip_early.xdc]
Parsing XDC File [/home/syshen/project_6/project_6.runs/impl_2/.Xil/Vivado-10925-svr641_7/dcp/chip.xdc]
Finished Parsing XDC File [/home/syshen/project_6/project_6.runs/impl_2/.Xil/Vivado-10925-svr641_7/dcp/chip.xdc]
Reading XDEF placement.
Reading XDEF routing.
Read XDEF File: Time (s): cpu = 00:00:00.73 ; elapsed = 00:00:00.74 . Memory (MB): peak = 1849.707 ; gain = 11.000
Restoring placement.
Restored 2622 out of 2622 XDEF sites from archive | CPU: 2.220000 secs | Memory: 20.855103 MB |
INFO: [Opt 31-138] Pushed 0 inverter(s).
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.

INFO: [Project 1-484] Checkpoint was created with build 881834
open_checkpoint: Time (s): cpu = 00:00:57 ; elapsed = 00:00:58 . Memory (MB): peak = 1857.707 ; gain = 1042.586
Attempting to get a license for feature 'Implementation' and/or device 'xc7vh580t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vh580t'
Running DRC as a precondition to command write_bitstream
INFO: [Drc 23-27] Running DRC with 8 threads
ERROR: [Drc 23-20] Rule violation (RTSTAT-2) Partially routed net - 2 net(s) are partially routed. The problem net(s) are inst_pll/inst/clk_out1, clkpma_tx_BUFG.
INFO: [Vivado 12-3199] DRC finished with 1 Errors, 2 Warnings, 1 Advisories
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
ERROR: [Vivado 12-1345] Error(s) found during DRC. Bitgen not run.
INFO: [Common 17-83] Releasing license: Implementation
write_bitstream: Time (s): cpu = 00:00:21 ; elapsed = 00:00:16 . Memory (MB): peak = 2065.227 ; gain = 207.520
ERROR: [Common 17-39] 'write_bitstream' failed due to earlier errors.

while executing
"write_bitstream -force chip.bit "
INFO: [Common 17-206] Exiting Vivado at Thu May 8 23:44:12 2014...

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Observer
Observer
6,432 Views
Registered: ‎10-03-2013

Hello,I have the same problem with LOCK_PINS because v7ht.tcl is read twice, bringing ERROR in opt_design.

If I move it, vivado synthesis makes an ERROR (could not find the file.. v7ht.tcl)

How to notify to vivado not to run twice v7ht.tcl ?

or where should I move it ?

 

Thank you

Arnaud.

 

 

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Visitor
Visitor
430 Views
Registered: ‎05-12-2019

hello 

do you know please how to freeze design in vivado

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