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Visitor
Visitor
3,362 Views
Registered: ‎06-07-2017

Critical Warning during Implementation

I have not placed instance design_1_i/clk_wiz_1/inst/clkin1_ibufgds at U8 then also I am getting below Critical Warning. Can someone please help me with this?

 

I am using KC705 evaluation board featuring the XC7K325T-2FFG900C FPGA.

 

[Vivado 12-1411] Cannot set LOC property of ports, Could not legally place instance design_1_i/clk_wiz_1/inst/clkin1_ibufgds at U8 (IPAD_X1Y10) since it belongs to a shape containing instance pcie_refclk_clk_n. The shape requires relative placement between design_1_i/clk_wiz_1/inst/clkin1_ibufgds and pcie_refclk_clk_n that can not be honoured because it would result in an invalid location for pcie_refclk_clk_n. ["/home/shubhamn/KINTEX_fpga_ethernet/KINTEX_fpga_ethernet.srcs/sources_1/bd/design_1/ip/design_1_clk_wiz_1_0/design_1_clk_wiz_1_0_board.xdc":3]

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Moderator
Moderator
3,354 Views
Registered: ‎09-15-2016

Hi @shubhamn

 

Please share your design to investigate further. Since U8 package pin is specific to pcie_clk port, not sure why the critical warning comes when you have not placed the  instance design_1_i/clk_wiz_1/inst/clkin1_ibufgds on it. 

 

Regards

Rohit

 

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Regards
Rohit
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Visitor
Visitor
3,351 Views
Registered: ‎06-07-2017

Below I have attached the design_1_wrapper_opt.dcp file of my project.

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Visitor
Visitor
3,350 Views
Registered: ‎06-07-2017

My major doubt is why I am not able to find U8 pin while allocating package pins to pcie_clkref_clk port.

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Xilinx Employee
Xilinx Employee
3,341 Views
Registered: ‎09-20-2012

Hi @shubhamn

 

U8 is dedicated MGTREFCLK pin. You have to instantiate IBUFDS_GTE2 instead of IBUFGDS if you want to use it to drive clock to fabric logic.  

Thanks,
Deepika.
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Visitor
Visitor
3,330 Views
Registered: ‎06-07-2017

Hi @vemulad

 

I have used D26 for pcie_refclk_clkp then also why I am getting the above error. I have not used U8.

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Xilinx Employee
Xilinx Employee
3,298 Views
Registered: ‎07-16-2008

When I opened the design checkpoint and exported the physical constraints, I noticed the following set_property commands.

set_property BOARD_PART_PIN pcie_mgt_clkp [get_ports pcie_refclk_clk_p]
set_property BOARD_PART_PIN pcie_mgt_clkn [get_ports pcie_refclk_clk_n]

 

This means the design top level ports pcie_refclk_clk_p/n automatically derive LOC and IOSTANDARD from board part pins pcie_mgt_clkp/n.

If you do 

get_property LOC [get_board_part_pins pcie_mgt_clkp]

it returns "U8".

 

You need to remove the BOARD_PART_PIN setting if not necessary.

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Visitor
Visitor
3,291 Views
Registered: ‎06-07-2017

Hi @graces

 

How to remove the BOARD_PART_PIN setting ?

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Xilinx Employee
Xilinx Employee
3,288 Views
Registered: ‎07-16-2008

The properties look to be set via IP xdc file.

design_1_clk_wiz_1_0_board.xdc

 

Is it the clocking wizard IP within a block design? Did you set board interface in IP customization?

You may want to re-visit the IP customization as the clock input is not used as GT pin.

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