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Observer
Observer
2,428 Views
Registered: ‎05-01-2018

[DRC 23-20] Rule violation (INBB-3) Black Box Instances

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I have a design with third party IP cores that were originally implemented using Xilinx ISE tool.  However, I'm using Vivado 2015.4 and it is giving me DRC black box errors during implementation.  Even after creating the ROMs in VIvado and replacing the old IPs with the latest IP, the errors continue. 

 

It changed from :

[DRC 23-20] Rule violation (INBB-3) Black Box Instances - Cell 'WJX_cs_top_inst/xLDPC_Decoder/swc_ldpc_dec_inst/U_LCD01GC/U_ROM/U_ROM01G0' of type 'WJX_cs_top_inst/xLDPC_Decoder/swc_ldpc_dec_inst/U_LCD01GC/U_ROM/U_ROM01G0/rom01g0' has undefined contents and is considered a black box.  The contents of this cell must be defined for opt_design to complete successfully.

 

to

[DRC 23-20] Rule violation (INBB-3) Black Box Instances - Cell 'WJX_cs_top_inst/xLDPC_Decoder/swc_ldpc_dec_inst/U_LCD01GC/U_ROM/U_ROM01G0' of type 'WJX_cs_top_inst/xLDPC_Decoder/swc_ldpc_dec_inst/U_LCD01GC/U_ROM/U_ROM01G0/xil_defaultlib_rom01g0' has undefined contents and is considered a black box.  The contents of this cell must be defined for opt_design to complete successfully.

 

Any help would be greatly appreciated.

Thanks,

Meera

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Moderator
Moderator
2,395 Views
Registered: ‎01-16-2013

@bmeera0,

 

The error is coming during opt_design which requires the design should not have any black box. 

Can you please recheck if the number of ports and instantiation name exactly matches in the RTL?

 

Also if you are running OOC run for IP, can you change it to Global and check the result.

 

--Syed

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Did you check our new quick reference timing closure guide (UG1292)?
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Moderator
Moderator
2,396 Views
Registered: ‎01-16-2013

@bmeera0,

 

The error is coming during opt_design which requires the design should not have any black box. 

Can you please recheck if the number of ports and instantiation name exactly matches in the RTL?

 

Also if you are running OOC run for IP, can you change it to Global and check the result.

 

--Syed

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------

View solution in original post

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Moderator
Moderator
2,382 Views
Registered: ‎05-08-2012

Hi @bmeera0. Is this a NGC netlist file? There are suggestions in the ISE to Vivado Migration Methodology Guide on page 9 that might help. One limitation is that Vivado does not support hierarchical NGC files.

 

http://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_1/ug911-vivado-migration.pdf#page=9

 

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