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Anonymous
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[DRC 23-20] Rule violation (REQP-1884) ODDR_has_invalid_load

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Implementation error :  I have used PLL to generate clock and oDDR to make clock more accurate on my custom IP. But when I implement that IP I get this error:  [DRC 23-20] Rule violation (REQP-1884) ODDR_has_invalid_load - ODDR cell PARALLEL_DAC_block_i/Sig_Gen_0/U0/ODDR_CLK loads should only be an output buffer or a port, but it is driving an invalid load (one or more of): oCLK_OBUF_inst, u_ila_0/inst/PROBE_PIPE.shift_probes_reg[0][15] and also 

Could anyone explain what did I do wrong?

Thank you

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Guide
Guide
12,957 Views
Registered: ‎01-23-2009

It looks like you tried to probe the forwarded clock with a Vivado Debugger ILA.

 

The message says that the output of the ODDR is connected to the oCLK_OBUF, which is correct (and what you see in your schematic), and is also connected to something in the u_ila_0/inst module, which is the standard name for the Vivado Debugger ILA.

 

This second connection probably doesn't appear in your schematic since the ILA Is inserted later in the tool flow.

 

You cannot probe this signal with an ILA - it is structurally illegal - the output of the ODDR must go only to the OBUF. It is also probably meaningless unless the ILA clock is significantly faster than the forwarded clock being generated by the ODDR (greater than 2x the frequency).

 

Avrum

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Xilinx Employee
Xilinx Employee
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Registered: ‎04-16-2012

Hi @Anonymous

 

Check the connectivity of ODDR output to know the reason of the error message.

From the error message, is states that ODDR output is connected to registers and other components whereas it should be connected to OBUF or a port.

 

Thanks,

Vinay

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Anonymous
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Thank you for quick reply @Vuppala for fast reply. I looked up in the synthesized design as shown in fig there is connection to OBUF instead of register.

syn_design.PNG

Also, new error came up at same point 

Vivado 12-4739] create_generated_clock:No valid object(s) found for '-source [get_pins PARALLEL_DAC_block_i/DDS_LUT_0/U0/ODDR_CLK/C]'. ["1/imports/Imports/Timing.xdc":1]

But I see the object on the synthesized figure.

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Highlighted
Guide
Guide
12,958 Views
Registered: ‎01-23-2009

It looks like you tried to probe the forwarded clock with a Vivado Debugger ILA.

 

The message says that the output of the ODDR is connected to the oCLK_OBUF, which is correct (and what you see in your schematic), and is also connected to something in the u_ila_0/inst module, which is the standard name for the Vivado Debugger ILA.

 

This second connection probably doesn't appear in your schematic since the ILA Is inserted later in the tool flow.

 

You cannot probe this signal with an ILA - it is structurally illegal - the output of the ODDR must go only to the OBUF. It is also probably meaningless unless the ILA clock is significantly faster than the forwarded clock being generated by the ODDR (greater than 2x the frequency).

 

Avrum

View solution in original post

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Registered: ‎11-09-2017

Hi, Did you find solution to tat problem ? Im having same issue just now :P 

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