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Newbie mac22
Newbie
294 Views
Registered: ‎09-19-2019

[DRC BIVC-1] Bank IO standard Vcc: Conflicting Vcc voltages in bank 34. For example, the following two ports in this bank have conflicting VCCOs: pwmsignal (LVCMOS18, requiring VCCO=1.800) and sw[7]

Hello. 

I am new to Vhdl and using Vivado. I have this error when I assign a pin in bank 34 for the FMC connector. 

It says there is a conflict between the pin assignment and switch assignment with the same bank because they have different VCCOs.

May you please kindly help on how I can solve this problem. 

Here is the error:

[DRC BIVC-1] Bank IO standard Vcc: Conflicting Vcc voltages in bank 34. For example, the following two ports in this bank have conflicting VCCOs:
pwmsignal (LVCMOS18, requiring VCCO=1.800) and sw[7] (LVCMOS33, requiring VCCO=3.300)

 

Thank you for your help in advance.

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1 Reply
Xilinx Employee
Xilinx Employee
279 Views
Registered: ‎05-22-2018

Re: [DRC BIVC-1] Bank IO standard Vcc: Conflicting Vcc voltages in bank 34. For example, the following two ports in this bank have conflicting VCCOs: pwmsignal (LVCMOS18, requiring VCCO=1.800) and s

Hi @mac22 ,

Error message indicates that there are conflicting IOSTANDARDs in one bank. Please check the below AR# link:

https://www.xilinx.com/support/answers/64450.html

Thanks,

Raj

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