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mohsin_ch
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Registered: ‎05-25-2018

DRC-ERRORS : DRC PLIDC-4 IDELAYCTRL IODELAYs with Conflicting groups for same Bank and DRC PLIDC-8 IDELAYCTRL missing for IODELAY

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I am cascading IDELAYe2 Modules for increasing the tap delay. I am facing DRC error during the Bit Stream in DRC. Its showing that IDELAYCTRL IODELAYs with conflicting groups for same bank. I am using Vivado 2017.4.

 

I have attached the DPC file, IDELAYCTRL Groups and DRC Errors list.

 

Please help me to solve the problem.

 

Regards,

Mohsin

IODELAY_IDELAYCTRL_ERRORS.PNG
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syedz
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@mohsin_ch

 

IDELAYCTRL of IODELAY_GROUP (MB_SUBSYSTEM_MIG_7SERIES_0_0_IODELAY_MIG0) was locked to different Clock region (X1Y0) than its IODELAY cells. I locked it to correct Clock region (X1Y2) after which the placement was successful. 

 

I used the attached test.tcl file to run placement in Vivado 2018.1. Also attached vivado.log file for your reference.

 

--Syed

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Did you check our new quick reference timing closure guide (UG1292)?
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mohsin_ch
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@syedzplease help me out. I have make a new thread as per your recommendations.

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mohsin_ch
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I am sending a Soft reminder to help me in that, as i am struck at that point and its urgency,

I am re sending the updated .dcp file for reviewing.

 

Regards,

Mohsin

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mohsin_ch
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Please @Deepika answer me.
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syedz
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@mohsin_ch

 

IDELAYCTRL of IODELAY_GROUP (MB_SUBSYSTEM_MIG_7SERIES_0_0_IODELAY_MIG0) was locked to different Clock region (X1Y0) than its IODELAY cells. I locked it to correct Clock region (X1Y2) after which the placement was successful. 

 

I used the attached test.tcl file to run placement in Vivado 2018.1. Also attached vivado.log file for your reference.

 

--Syed

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------

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mohsin_ch
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Please guide me how can i locked IODELAYGROUP(MB_SUBSYSTEM_MIG_7SERIES_0_0_IODELAY_MIG0) to correct clock region of X1Y2?

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syedz
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@mohsin_ch,

 

I have sent you the files from ezmove. Please check.

 

--Syed

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mohsin_ch
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Registered: ‎05-25-2018

Dear Zubair,

 

Please guide me how it can be found that mb_subsystem_i/mig_7series_0/u_mb_subsystem_mig_7series was locked to wrong clock region?

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mohsin_ch
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Dear Syed Zubair,

 

The problem is resolved, by the procedure you followed.

 

Regards,

Mohsin

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mohsin_ch
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Dear Zubair,

 

My question is left behind, Please guide me how it can be found that mb_subsystem_i/mig_7series_0/u_mb_subsystem_mig_7series was locked to wrong clock region? It will be helpfull to me in my next Xilinx project.

 

Regards,

Mohsin

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syedz
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@mohsin_ch,

 

You can use place_ports command to run the clock and I/O placement step first. Then run place_design. If port placement fails, the placement is saved to memory to allow failure analysis. For more information, run place_ports -help from the Vivado Tcl command prompt.

 

--Syed

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mohsin_ch
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I run the Place_ports command. In Phase 1, Its add constraints, add user pBlocks. In Phase 2, IO and CLK Clean up and Fix them.

In Place_design, Its placed the corrected blocks.

 

Because the placement was already corrected, its didn't give any error. If, in case, the placement is not corrected, how can we perform failure analysis? Still, i didn't get the idea. If there is any document, please refer me.

 

Best Regards,

Mohsin

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syedz
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@mohsin_ch,

 

You can refer to UG904 "Implementation" user guide :

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_2/ug904-vivado-implementation.pdf

 

--Syed

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mohsin_ch
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Ok. Thanks

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