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Visitor
Visitor
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Registered: ‎06-05-2020

[DRC LUTLP-1] Combinatorial Loop Alert. But I didn`t find this feedback loop.

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Hi All,

I encountered an error in the Generate Bitstream with vivado 2019.1.

The following is the error message:

[DRC LUTLP-1] Combinatorial Loop Alert: 5 LUT cells form a combinatorial loop. This can create a race condition. Timing analysis may not be accurate. The preferred resolution is to modify the design to remove combinatorial logic loops. If the loop is known and understood, this DRC can be bypassed by acknowledging the condition and setting the following XDC constraint on any one of the nets in the loop: 'set_property ALLOW_COMBINATORIAL_LOOPS TRUE [get_nets <myHier/myNet>]'. One net in the loop is Is1/Imod/Iccu6/It0/Iregbuf/I154/q_reg[11]_0. Please evaluate your design. The cells in the loop are: Is1/Imod/Iccu6/It0/Iregbuf/I189/q[19]_i_4, Is1/Imod/Iccu6/It2/Iregbuf/I189/q[19]_i_4__0, Is1/Imod/Iccu6/It1/Iregbuf/I189/q[19]_i_4__6, Is1/Imod/Iccu6/It0/Iregbuf/I154/q[19]_i_7, and Is1/Imod/Iccu6/It1/Iregbuf/I154/q[19]_i_8.

I read some posts. Someone says this message is informing you that there is a feedback loop in my combinational circuit, like this

fdbk.png

 

 

 

 

But the error I see is like this

 

error.png

 

Just a line. I can`t find the reason.

 

Can you please guide me on how to resolve the issue.

 

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Xilinx Employee
Xilinx Employee
447 Views
Registered: ‎06-27-2018

Hi @yanxj,

To get a clean schematic of loop, follow below steps:-

  1. Select all the pins (ctrl+A) in the loops section and press F4.
  2. Now you will see a schematic of all the LUTs with pin selected, right click on one of the pin in schematic and select Expand cone -> To selected cells

      forum1.png

     3. Now regenerate schematic and you will be able to see a neat schematic of the loop in design.

      forum2.png

 

~Chinmay

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Xilinx Employee
Xilinx Employee
545 Views
Registered: ‎01-30-2019

Hi @yanxj ,

Open your synthesized design and do a check_timing to see if there are combinatorial loops present in your Synthesized design. Run the command mentioned below to find the same.

check_timing -exclude {no_clock constant_clock pulse_width_clock unconstrained_internal_endpoints no_input_delay no_output_delay multiple_clock generated_clocks partial_input_delay partial_output_delay latch_loops } -verbose -name timing_1

If the Loops are present in your design after synthesis itself then you need to make changes to your design in order to fulfil the DRC and avoid combinatorial loops.

Else if the loops are not present in your design after synthesis then it is possible that due to some optimization during Implementation, the tool introduced the loops in your design. In this case, simply FIND the primitives forming the loop using the above command, then select the primitive and look for a property like OPT_MODIFIED, PHY_OPT_MODIFIED, etc in the Properties window.

If this is not the case then further analysis is needed, please do the above checks so that we can go for further analysis.

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Visitor
Visitor
522 Views
Registered: ‎06-05-2020

hi, @surajc 

Thank you for your reply.

Yes, I see the error in my Synthesized design.

But is there a command to mark the entire loop at Schematic?

Why is it marked with a Pin instead of the entire loop or cell? Like this link https://wiki.nus.edu.sg/display/EE2020DP/%5BDRC+23-20%5D+Rule+violation+%28LUTLP-1%29+Combinatorial+Loop

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Xilinx Employee
Xilinx Employee
508 Views
Registered: ‎01-30-2019

Hi @yanxj ,

If you run the check_timing command without the -name option in the tcl console, The tool will dump out the hierarchical names of the pins forming the combinatorial loop. 

Since it is a loop, one cell will be listed twice, one time stating the input pin and second time stating the output pin.

Simply remove the name of the pin from the end and you will get the name of the cell. 

e.g. if the tcl console dumps top/mod_a/sub_mod.a/LUT4/I0 ( part in bold is the cell name and the other is the name of the pin of the cell)

you can then use the cell name to find schematic.

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Visitor
Visitor
460 Views
Registered: ‎06-05-2020

Hi, @surajc 

Thank you for your reply.

This is the result of running the check_timing command.

pins.png

 

 

So, the loop is between I154 and I189, or q[19]_i_7, q[19]_i_4, q[19]_i_4_0 and q[19]_i_4_6. Which is more accurate?

And, are there the loops inside every cell (e.g. I189, q[19]_i_7), or is there the loop between these cells.

 

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Highlighted
Xilinx Employee
Xilinx Employee
448 Views
Registered: ‎06-27-2018

Hi @yanxj,

To get a clean schematic of loop, follow below steps:-

  1. Select all the pins (ctrl+A) in the loops section and press F4.
  2. Now you will see a schematic of all the LUTs with pin selected, right click on one of the pin in schematic and select Expand cone -> To selected cells

      forum1.png

     3. Now regenerate schematic and you will be able to see a neat schematic of the loop in design.

      forum2.png

 

~Chinmay

View solution in original post

Highlighted
Visitor
Visitor
432 Views
Registered: ‎06-05-2020

Hi, @chinmays 

This is really a good way. I found this loop, It looks very intuitive.

Thank you for your way.

And, Thanks for your guidance @surajc, let me found the loop. 

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