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Visitor siddharth_m
Visitor
294 Views
Registered: ‎08-18-2019

[DRC MDRV-1] Net <const0> has multiple drivers

Hi,

I am trying to read and write to DDR3 using MIG 7 series on an Opal Kelly xem7310. I continue to get this error during implementation. I removed all of my design except for the IP core and its wrapper and I still get this error. I checked all the outputs of the MIG and made sure it is not being driven in my top module as well. I'm not sure how to fix this, any help would be appreciated.

Thanks!

3 Replies
Xilinx Employee
Xilinx Employee
284 Views
Registered: ‎05-22-2018

Re: [DRC MDRV-1] Net <const0> has multiple drivers

Hi @siddharth_m ,

This message is informing you that there is a signal (in the error example above, signal y is the source of the error) that is being assigned / updated / driven in two different always blocks.

An example of a piece of code that would generate such an error is shown below:

always @ (posedge CLK)

y = y + 1;

 

always @ (posedge CLK2)
y = y + 3;

In the example code above, there are two conflicting instructions presented. The first instruction would be to increment y by 1, while the second instruction would be to increment y by 3. The compiler would not be able to know which instruction should be executed. Thus, the Multiple Driver Nets error would occur.

To solve this error, examine your code and the error to first identiy 

To solve this error :
  1. Examine the error to first identify the signal (for example signal y) with multiple conflicting drivers.
    1. In cases of large and complex designs, it may be easier to use the elaborated netlist (RTL Analysis → Open Elaborated Design) to identify the signal.
  2. Within the always blocks in your code, search for lines of code where y is the target of assignment (y <= ... or y = ...) to identify the multiple drivers.
  3. Modify the code and remove this issue.

Thanks,

Raj

Visitor siddharth_m
Visitor
234 Views
Registered: ‎08-18-2019

Re: [DRC MDRV-1] Net <const0> has multiple drivers

Thanks @rshekhaw ! That helped me locate the issue but I am still clueless as to how to solve this. So I found that the following input/inout signals to the MIG are all connected to GND: app_addr, app_ref_req, app_sr_req, app_wdf_data, app_wdf_mask, app_zq_req, ddr3_dq, ddr3_dqs_p, ddr3_dqs_n. So for example when I use app_addr to set the data or app_wdf_data for data, I believe it is driven by my logic as well as GND. I don't understand why these signals are tied to ground and what changes do I have to make while generating the MIG ip core? 

0 Kudos
Xilinx Employee
Xilinx Employee
184 Views
Registered: ‎05-08-2012

Re: [DRC MDRV-1] Net <const0> has multiple drivers

Hi @siddharth_m 

It might be helpful to take the same IP XCI file, and generate an example design (right-click -> Open in Example Design). From this, you can compare what is different. I suspect that there might be unconnected IP ports related to the error. The open elaborated design would be the best stage to view this.

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