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Visitor
Visitor
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Registered: ‎06-11-2019

[DRC PDCY-4] CARRY4 unconnected input

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Hi guys,

I have a problem when connecting a customized AXI4 peripheral to a Zynq processor. After building and validating the the block design (no errors found), I ran Generate Bitstream in order to export my design to Vitis but got the following error.

[DRC PDCY-4] CARRY4 unconnected input: CARRY input pin(s) design_1_i/KI_IP_128_0/inst/KI_IP_128_v1_0_S00_AXI_inst/UUP/genblk1[0].A/axi_rdata_reg[10]_i_187/DI[2], design_1_i/KI_IP_128_0/inst/KI_IP_128_v1_0_S00_AXI_inst/UUP/genblk1[0].A/axi_rdata_reg[10]_i_187/DI[1], and design_1_i/KI_IP_128_0/inst/KI_IP_128_v1_0_S00_AXI_inst/UUP/genblk1[0].A/axi_rdata_reg[10]_i_187/DI[0] are unconnected. These pins must be connected to a signal or tied to VCC or GND when output pin design_1_i/KI_IP_128_0/inst/KI_IP_128_v1_0_S00_AXI_inst/UUP/genblk1[0].A/axi_rdata_reg[10]_i_187/O[3] is used.

Could someone please explain me what it means? Have any of you faced the same problem? At first I thought I had run out of resources but it is not the case. I  checked both the RTL analysis and the synthesized design and at first glance they are both correct. 

Thank you very much in advance.

 

Juan.

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Xilinx Employee
Xilinx Employee
208 Views
Registered: ‎05-22-2018

Re: [DRC PDCY-4] CARRY4 unconnected input

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Hi @nadales ,

This DRC reports that the particular mentioned CARRY4 input is not connected in your design,

you can open the synthesized design and search for the CARRY4 mentioned in the errror,

or run the below commad to find the CARRY4 with unconnected input directly:

set pins_list [get_pins -filter { DIRECTION == "IN" && NAME =~  "*DI*" &&  IS_CONNECTED == "FALSE" } -of_objects  [get_cells -hierarchical -filter { PRIMITIVE_TYPE == CARRY.OTHERS.CARRY4 }]]

Also you can directly connect them to ground if not needed:

connect_net -hier -net [get_nets <const0>] -objects {[$pins_list]}

Thanks,

Raj

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Xilinx Employee
Xilinx Employee
209 Views
Registered: ‎05-22-2018

Re: [DRC PDCY-4] CARRY4 unconnected input

Jump to solution

Hi @nadales ,

This DRC reports that the particular mentioned CARRY4 input is not connected in your design,

you can open the synthesized design and search for the CARRY4 mentioned in the errror,

or run the below commad to find the CARRY4 with unconnected input directly:

set pins_list [get_pins -filter { DIRECTION == "IN" && NAME =~  "*DI*" &&  IS_CONNECTED == "FALSE" } -of_objects  [get_cells -hierarchical -filter { PRIMITIVE_TYPE == CARRY.OTHERS.CARRY4 }]]

Also you can directly connect them to ground if not needed:

connect_net -hier -net [get_nets <const0>] -objects {[$pins_list]}

Thanks,

Raj

View solution in original post

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Visitor
Visitor
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Registered: ‎06-11-2019

Re: [DRC PDCY-4] CARRY4 unconnected input

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Thanks, it worked! Problem solved.

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