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Visitor lcs86
Visitor
185 Views
Registered: ‎03-13-2014

[DRC REQP-1576]Clock output performance paths: Unsupported MMCME2_ADV connectivity.

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After implementation, I run generate bitstream. And I got the message with this error.

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[DRC REQP-1576] Clock output performance paths: Unsupported MMCME2_ADV connectivity. The signal zsys_i/...../U10_MMCM/inst/clk_out3b_MMCM on the zsys_i/...../U10_MMCM/inst/mmcm_adv_inst/CLKOUT2B pin of zsys_i/..../U10_MMCM/inst/mmcm_adv_inst does not use dedicated connectivity. Routing from this pin to other than a BUFG or BUFH buffer type uses a non-performance path. Use CLKOUT0-3 instead or useCLOCK_DEDICATED_ROUTE constraint on the net. Note: using the CLOCK_DEDICATED_ROUTE option may not be sufficient to achieve this routing.

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This design is comprised of multi-phase MMCM and used ISERDESE2 / IDELAYE2.

Please let me know the solution of this error.

Thank you.

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1 Solution

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Xilinx Employee
Xilinx Employee
163 Views
Registered: ‎07-16-2008

回复: [DRC REQP-1576]Clock output performance paths: Unsupported MMCME2_ADV connectivity.

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It looks you connect CLKOUT2B to load pin other than BUFG/BUFH.I. e.g. route CLKOUT2B to BUFR/BUFIO

Just as the error points out, this is not a supported connectivity. Below is referenced from UG472,

High-Performance Clocks

7 series FPGAs contain four HPCs per I/O bank. These clocks are a direct short differential connection to BUFIOs and BUFRs in the I/O. Therefore, these clocks exhibit very low jitter and minimal duty-cycle distortion. In the I/O columns, the HPC connects to the BUFIO/BUFRs and drives the I/O logic. Since the CMT column is co-located next to the I/O column, the HPC drives directly into the I/O bank next to a CMT.

HPCs are driven by CLKOUT[3:0] of the MMCM (only).

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3 Replies
Xilinx Employee
Xilinx Employee
167 Views
Registered: ‎02-27-2019

回复: [DRC REQP-1576]Clock output performance paths: Unsupported MMCME2_ADV connectivity.

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Could you provide the connection of the MMCM? Screenshot or code.

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Xilinx Employee
Xilinx Employee
164 Views
Registered: ‎07-16-2008

回复: [DRC REQP-1576]Clock output performance paths: Unsupported MMCME2_ADV connectivity.

Jump to solution

It looks you connect CLKOUT2B to load pin other than BUFG/BUFH.I. e.g. route CLKOUT2B to BUFR/BUFIO

Just as the error points out, this is not a supported connectivity. Below is referenced from UG472,

High-Performance Clocks

7 series FPGAs contain four HPCs per I/O bank. These clocks are a direct short differential connection to BUFIOs and BUFRs in the I/O. Therefore, these clocks exhibit very low jitter and minimal duty-cycle distortion. In the I/O columns, the HPC connects to the BUFIO/BUFRs and drives the I/O logic. Since the CMT column is co-located next to the I/O column, the HPC drives directly into the I/O bank next to a CMT.

HPCs are driven by CLKOUT[3:0] of the MMCM (only).

-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

View solution in original post

Visitor lcs86
Visitor
151 Views
Registered: ‎03-13-2014

回复: [DRC REQP-1576]Clock output performance paths: Unsupported MMCME2_ADV connectivity.

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Thank you for your reply.

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