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Explorer
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Registered: ‎11-13-2009

DRC REQP-1853 Cascaded clock buffers with constant CE?

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I see this DRC warning and wanted to understand the correct usage of the BUFGCE_DIV module.

My usage is to create a simple divide by 2 clock because I have some IP that doesn't run at our full clock rate.  I don't have access to the centralized clock generation as it comes from external design block I am not allowed to alter.

So my solution was just instantiate a BUFGCE_DIV in my module.  Now I see this warning that indicates "may result in large clock skew and timing violations." I am trying to understand the conditions in which it may not be a timing issue.  Can someone suggest the proper usage of this BUFGCE_DIV module?

TomT...

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Registered: ‎01-22-2015

Re: DRC REQP-1853 Cascaded clock buffers with constant CE?

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@tessitd

The BUFGCE_DIV is found in UltraScale FPGAs. As stated in UG949 (on about page 81), BUFGCE_DIV is often used as a replacement for the BUFR found in 7-series FPGAs. By this, I think UG949 means that the BUFGCE_DIV and the BUFR can both be used to divide-down clocks.

As you can imagine, these divide-down buffers have a built-in counter. Ideally, when you power-up the FPGA, the main Clock Management Tile (eg. MMCM) starts outputting clocks and the built-in counter inside the BUFGCE_DIV starts at zero. In this way, clocks coming out of the MMCM and the clock coming out of the BUFGCE_DIV start up with a known phase relationship, which is necessary if timing analysis is to consider all the clocks to be synchronous.

However, if you start/stop the BUFGCE_DIV output using the CE pin then the phase of the clock coming out of the BUFGCE_DIV is no longer known with respect to the other clocks in your design (because the built-in counter of the BUFGCE_DIV gets messed up). This means that the BUFGCE_DIV output clock (call it CLK_BD) is now mesochronous with other clocks in your design. Thus, you need a clock crossing circuit to prevent metastability when moving data in/out of the CLK_BD clock-domain from/to other clock-domains.

Apparently, there are procedures for resetting things so that CLK_BD is again synchronous (and not mesochronous) with other clocks in the design - as when the FPGA was powered-up. However, I have not found a good explanation of these procedures. The best I’ve found is in UG472 (v1.14) immediately below Fig. 2-25. You’ll also find this discussed by Avrum in <this> post.

Anyway, I suspect that REQP-1853 may be warning you to treat the BUFGCE_DIV output clock as a mesochronous (or an asynchronous) – and to use a clock crossing circuit.

Cheers,
Mark

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Xilinx Employee
Xilinx Employee
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Registered: ‎05-08-2012

Re: DRC REQP-1853 Cascaded clock buffers with constant CE?

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Hi @tessitd. The skew can come about if there is a cross domain crossing where the destination clock is different from the source clock. In that case if the source clock has the two BUFGCE_DIVs in the path, but the destination only has one or zero, there will be clock skew delay found in the timing report.


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Registered: ‎01-22-2015

Re: DRC REQP-1853 Cascaded clock buffers with constant CE?

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@tessitd

The BUFGCE_DIV is found in UltraScale FPGAs. As stated in UG949 (on about page 81), BUFGCE_DIV is often used as a replacement for the BUFR found in 7-series FPGAs. By this, I think UG949 means that the BUFGCE_DIV and the BUFR can both be used to divide-down clocks.

As you can imagine, these divide-down buffers have a built-in counter. Ideally, when you power-up the FPGA, the main Clock Management Tile (eg. MMCM) starts outputting clocks and the built-in counter inside the BUFGCE_DIV starts at zero. In this way, clocks coming out of the MMCM and the clock coming out of the BUFGCE_DIV start up with a known phase relationship, which is necessary if timing analysis is to consider all the clocks to be synchronous.

However, if you start/stop the BUFGCE_DIV output using the CE pin then the phase of the clock coming out of the BUFGCE_DIV is no longer known with respect to the other clocks in your design (because the built-in counter of the BUFGCE_DIV gets messed up). This means that the BUFGCE_DIV output clock (call it CLK_BD) is now mesochronous with other clocks in your design. Thus, you need a clock crossing circuit to prevent metastability when moving data in/out of the CLK_BD clock-domain from/to other clock-domains.

Apparently, there are procedures for resetting things so that CLK_BD is again synchronous (and not mesochronous) with other clocks in the design - as when the FPGA was powered-up. However, I have not found a good explanation of these procedures. The best I’ve found is in UG472 (v1.14) immediately below Fig. 2-25. You’ll also find this discussed by Avrum in <this> post.

Anyway, I suspect that REQP-1853 may be warning you to treat the BUFGCE_DIV output clock as a mesochronous (or an asynchronous) – and to use a clock crossing circuit.

Cheers,
Mark

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