cancel
Showing results for 
Search instead for 
Did you mean: 
Visitor
Visitor
10,980 Views
Registered: ‎12-07-2012

Difference between Map and Place

Jump to solution

So can anyone explain what difference between Map and Place? I can understand that synthesis is translation vhdl or verilog to RTL model, I can understand that Translate is converting the RTL primitives to Xilinx primitives (for axample "and gate" to LUT2), I can also understand that Route is connectiong placed primitives on FPGA(such LUT6), but who do placement: Map or Place? If Place, then what do Map? I can't find clear description of this processes in documentation.

Tags (2)
0 Kudos
1 Solution

Accepted Solutions
Highlighted
Guide
Guide
16,924 Views
Registered: ‎01-23-2009

Re: Difference between Map and Place

Jump to solution

You have to realize that these programs have been around for a while, and their purposes have changed somewhat over time.

 

Synthesis (i.e. XST or Synplify) converts an RTL description of your design (Verilog/VHDL) into a netlist of Xilinx Basic ELements (BELs). These are flip-flops, LUTs, wide mux elements, carry chain elements, distributed RAMs, block RAMs, DSP cells, I/O components (IBUF, OBUF, OBUFT, IOBUF, IDDR, ODDR, ISERDES, OSERDES), and clocking elements (BUFG, BUFR, BUFIO, BUFH, PLL, MMCM, DCM), etc...

 

The ngdbuild program mostly does bringing things together and cleanup. You may have synthesized your design in several parts, you may have IP that needs to be linked in, and you have constraints (UCF) that need to be added to the design. ngdbuild puts all this together, does cleanup (removing unconnected things), does some constraint propagation (i.e. through MMCMs, etc...) and writes everything out into a single file.

 

The purpose of MAP has changed over time. Originally MAP did "packing" - the real placeable element on the Xilinx FPGA is the slice, which contains multiple LUTs, FFs, wide mux elements, and carry chains. MAP originally took the netlist of BELs and converted them to a netlist of slices, which was used by the rest of the processes.

 

Once the design was mapped (in the olden days) then it would go on to PAR, which is place and route. The placer would place the slices into locations, and the router would make the connections between them.

 

However, over time, the relationship between MAP and PAR changed. Now, (the inaccurately named) MAP does the packing and also does the placement - thus resulting in a placed .ncd file as the output of MAP. Once placed, the (now inaccurately named) PAR only routes the design.

 

So:

  XST: synthesis

  NGDBUILD: linking everything together and cleanup

  MAP: Packing and placement

  PAR: Routing

  TRCE: Final timing report generation

  BITGEN: Generation of a bitstream

 

Avrum

View solution in original post

5 Replies
Highlighted
Xilinx Employee
Xilinx Employee
10,977 Views
Registered: ‎08-02-2007

Re: Difference between Map and Place

Jump to solution

Hi,

 

Refer to the link http://www.xilinx.com/support/documentation/sw_manuals/xilinx11/ise_c_implement_fpga_design.htm

 

--Hem

----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------
0 Kudos
Highlighted
Visitor
Visitor
10,975 Views
Registered: ‎12-07-2012

Re: Difference between Map and Place

Jump to solution

Hi! Thanks, but I have already seen that, it not clear for me.

"The Map process maps the logic defined by an NGD file into FPGA elements, such as CLBs and IOBs" - so here LUT2 convertet to lut6 and take his own place in slice (e.g. x0y0) in some CLB ? Or somesing else?

"The Place and Route places and routes the design" - very nice description ;)

0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
10,970 Views
Registered: ‎08-02-2007

Re: Difference between Map and Place

Jump to solution

hi,

 

Translate generates a ngd file.

 

MAP looks at the ngd and maps the elements in the netlist to the primitives available in the FPGA.

 

For example, FF's to Slices; Memory Blocks to RAMB's 

 

These elements are then placed and routed to make sure that the timing is met.

 

Refer to a post http://forums.xilinx.com/t5/Synthesis/difference-between-synthesis-and-map-process/td-p/126522

 

--Hem

----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------
0 Kudos
Highlighted
Guide
Guide
16,925 Views
Registered: ‎01-23-2009

Re: Difference between Map and Place

Jump to solution

You have to realize that these programs have been around for a while, and their purposes have changed somewhat over time.

 

Synthesis (i.e. XST or Synplify) converts an RTL description of your design (Verilog/VHDL) into a netlist of Xilinx Basic ELements (BELs). These are flip-flops, LUTs, wide mux elements, carry chain elements, distributed RAMs, block RAMs, DSP cells, I/O components (IBUF, OBUF, OBUFT, IOBUF, IDDR, ODDR, ISERDES, OSERDES), and clocking elements (BUFG, BUFR, BUFIO, BUFH, PLL, MMCM, DCM), etc...

 

The ngdbuild program mostly does bringing things together and cleanup. You may have synthesized your design in several parts, you may have IP that needs to be linked in, and you have constraints (UCF) that need to be added to the design. ngdbuild puts all this together, does cleanup (removing unconnected things), does some constraint propagation (i.e. through MMCMs, etc...) and writes everything out into a single file.

 

The purpose of MAP has changed over time. Originally MAP did "packing" - the real placeable element on the Xilinx FPGA is the slice, which contains multiple LUTs, FFs, wide mux elements, and carry chains. MAP originally took the netlist of BELs and converted them to a netlist of slices, which was used by the rest of the processes.

 

Once the design was mapped (in the olden days) then it would go on to PAR, which is place and route. The placer would place the slices into locations, and the router would make the connections between them.

 

However, over time, the relationship between MAP and PAR changed. Now, (the inaccurately named) MAP does the packing and also does the placement - thus resulting in a placed .ncd file as the output of MAP. Once placed, the (now inaccurately named) PAR only routes the design.

 

So:

  XST: synthesis

  NGDBUILD: linking everything together and cleanup

  MAP: Packing and placement

  PAR: Routing

  TRCE: Final timing report generation

  BITGEN: Generation of a bitstream

 

Avrum

View solution in original post

Highlighted
Visitor
Visitor
10,953 Views
Registered: ‎12-07-2012

Re: Difference between Map and Place

Jump to solution

0 Kudos