Different Timing report in Summary and Post-PAR Static timing report

[milan_mian]

Hi, I was implementing one of our projects here in Xilinx ISE 14.6. We got following project status:

Design Overview -- Summary

 => Errors : No Errors

=> Warnings : 7500 Warnings

=> Routing Results: All signals Completely Routed

=> Timing Constraints: All Constraints Met

=> Final Timing Score: 0 (Timing Report).

So, all constraints are met with no timing errors. But, when I checked post-PAR static timing report,

I got following :

Timing summary:
---------------

Timing errors: 216 Score: 239257 (Setup/Max: 0, Hold: 239257)

Constraints cover 1016835555557 paths, 0 nets, and 135979 connections

Design statistics:
Minimum period: 19.913ns (Maximum frequency: 50.218MHz)
Maximum combinational path delay: 21.363ns
Maximum path delay from/to any node: 19.913ns
Minimum input required time before clock: 13.015ns
Maximum output delay after clock: 24.091ns.

Could somebody kindly explain me the reason for this or ways to fix these errors?

Thanks.

[balkris]

You can use the  SmartXplorer for better timing report

The unconstrained timing report may include hold errors that are not explicitly covered by user timing constraints. 

For more information on this issue, pleas see (Xilinx Answer 37292) 

[yashp]

Hi,

Is report unconstrained paths OR -U is enabled in TRACE?
This might be the reason of difference in summary and report.
Because summary shows the results of user constraints but timing report is giving more details as per switch/settings used by user.

Is it possible for you to share timing report?
Also you can check the paths which shows violations analyzed under which constraints? or it is unconstrained.

Thanks,
Yash

[milan_mian]

Thanks for your answers. 

Could the uncontrained path's hold errors giving me this errors?

================================================================================
Timing constraint: Unconstrained path analysis
31045 paths analyzed, 26771 endpoints analyzed, 216 failing endpoints
216 timing errors detected. (0 setup errors, 216 hold errors)
Minimum period is 13.224ns.
Maximum delay is 21.363ns.
-------------------------------------------------------------------------------

Thank you.

[nagabhar]

HI @milan_mian

Yes it is possible. 
As the hold analysis happens  from an edge  and to the same edge,The tool can do Hold  timing analysis  on unconstrained  paths as it does need an explicit time spec constraint  that specifies clock period.

Can you share the complete  timing report so that we can confirm the same.