08-24-2016 07:25 AM
Hi, I was implementing one of our projects here in Xilinx ISE 14.6. We got following project status:
Design Overview -- Summary
=> Errors : No Errors
=> Warnings : 7500 Warnings
=> Routing Results: All signals Completely Routed
=> Timing Constraints: All Constraints Met
=> Final Timing Score: 0 (Timing Report).
So, all constraints are met with no timing errors. But, when I checked post-PAR static timing report,
I got following :
Timing summary:
---------------
Timing errors: 216 Score: 239257 (Setup/Max: 0, Hold: 239257)
Constraints cover 1016835555557 paths, 0 nets, and 135979 connections
Design statistics:
Minimum period: 19.913ns (Maximum frequency: 50.218MHz)
Maximum combinational path delay: 21.363ns
Maximum path delay from/to any node: 19.913ns
Minimum input required time before clock: 13.015ns
Maximum output delay after clock: 24.091ns.
Could somebody kindly explain me the reason for this or ways to fix these errors?
Thanks.
08-24-2016 07:38 AM
You can use the SmartXplorer for better timing report
The unconstrained timing report may include hold errors that are not explicitly covered by user timing constraints.
For more information on this issue, pleas see (Xilinx Answer 37292)
08-24-2016 10:12 AM
08-25-2016 04:47 AM - edited 08-25-2016 04:48 AM
Thanks for your answers.
Could the uncontrained path's hold errors giving me this errors?
================================================================================
Timing constraint: Unconstrained path analysis
31045 paths analyzed, 26771 endpoints analyzed, 216 failing endpoints
216 timing errors detected. (0 setup errors, 216 hold errors)
Minimum period is 13.224ns.
Maximum delay is 21.363ns.
-------------------------------------------------------------------------------
Thank you.
08-29-2016 10:22 AM - edited 08-29-2016 10:23 AM
HI @milan_mian
Yes it is possible.
As the hold analysis happens from an edge and to the same edge,The tool can do Hold timing analysis on unconstrained paths as it does need an explicit time spec constraint that specifies clock period.
Can you share the complete timing report so that we can confirm the same.