Different logic utilization after synthesis and implementation

[zhimengfan1990]

Dear everyone, I find my design utilization different resources between synthesis and implementation.

Utilization after synthesis:

Utilization after implementation:

My question is why there is such a big different between two steps?

More curiously, the netlist after implementation is incomplete. Since I have a generate for statement in the design, loops are from 0 to 57, but the netlist displays only the cell for index 0, other cells from 1 to 57 are all missing. How can this be?

 

Thanks at first!

[pratham]

Hello @zhimengfan1990,

Can you attach your vivado .log here? can you check for warnings about trimming of the logic?

[vemulad · Accepted solution]

Hi,

There could be trimming happening during Implementation.

Refer to page-53 of http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_4/ug904-vivado-implementation.pdf for the different kinds of optimizations performed during implementation.

Thanks,

Deepika.

[zhimengfan1990]

Thank you very much! I just found a similar post: http://forums.xilinx.com/t5/Implementation/Vivado-Implementation-Some-Logic-Missing/m-p/392947/highlight/true#M7622 .

It's true that some "unconnected" nets are eliminated. But the eliminated codes are not "unconnected". I wonder if the logic optimization tool mis-operated? 

Any way, thank you for your reply!  :-)