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zhimengfan1990
Observer
Observer
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Registered: ‎05-04-2015

Different logic utilization after synthesis and implementation

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Dear everyone, I find my design utilization different resources between synthesis and implementation.

 

Utilization after synthesis:

a.png

 

Utilization after implementation:

b.png

 

My question is why there is such a big different between two steps?

More curiously, the netlist after implementation is incomplete. Since I have a generate for statement in the design, loops are from 0 to 57, but the netlist displays only the cell for index 0, other cells from 1 to 57 are all missing. How can this be?

 c.png

 

Thanks at first!

 

 

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vemulad
Xilinx Employee
Xilinx Employee
15,005 Views
Registered: ‎09-20-2012

Hi,

 

There could be trimming happening during Implementation.

 

Refer to page-53 of http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_4/ug904-vivado-implementation.pdf for the different kinds of optimizations performed during implementation.

 

Thanks,

Deepika.

Thanks,
Deepika.
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pratham
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Registered: ‎06-05-2013

Hello @zhimengfan1990,

Can you attach your vivado .log here? can you check for warnings about trimming of the logic?

-Pratham

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vemulad
Xilinx Employee
Xilinx Employee
15,006 Views
Registered: ‎09-20-2012

Hi,

 

There could be trimming happening during Implementation.

 

Refer to page-53 of http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_4/ug904-vivado-implementation.pdf for the different kinds of optimizations performed during implementation.

 

Thanks,

Deepika.

Thanks,
Deepika.
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zhimengfan1990
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Registered: ‎05-04-2015

Thank you very much! I just found a similar post: http://forums.xilinx.com/t5/Implementation/Vivado-Implementation-Some-Logic-Missing/m-p/392947/highlight/true#M7622 .

 

It's true that some "unconnected" nets are eliminated. But the eliminated codes are not "unconnected". I wonder if the logic optimization tool mis-operated? 

 

Any way, thank you for your reply!  :-)

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