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Visitor
Visitor
19,679 Views
Registered: ‎02-10-2016

ERROR: [DRC 23-20] Rule violation (INBB-3) Black Box Instances

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Hello,

I'm working with a tcl driven Vivado build-flow and I'm getting an error message during opt_design:

ERROR: [DRC 23-20] Rule violation (INBB-3) Black Box Instances  - Cell 'mig' of type 'mig/mig_0' has undefined contents and is considered a black box. The contents of this cell must be defined for opt_design to complete successfully.

ERROR: [Vivado_Tcl 4-78] Error(s) found during DRC. Opt_design not run.

 

The tcl script does the following:

1. creates the project

2. imports IP (as .xci files via import_ip

3. generates the IP (via: generate_target all [get_files mig_0.xci] -force )
4. synthesizes the design (via: synth_design -top $design_top -part $device -flatten_hierarchy rebuilt )

5. opt_design   <-- this is when the error shows.

 

However, when I press the Run Implementation button in Vivado afterwards the process (incl. the opt_design step) completes just fine. It only fails when I try to run Implementation though the tcl script. How can I fix this?

 

Thank you for your support.

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Xilinx Employee
Xilinx Employee
35,973 Views
Registered: ‎09-20-2012

Hi @arnold80

 

Are you using project mode or non-project mode when running using TCL?

 

It looks like you are combining the project mode and non project mode commands.

 

If you want to use project mode then use the below commands

 

add_files ip_name.xci or import_files

generate_target all [get_ips ip_name]

create_ip_run [get_ips ip_name]

launch_runs [get_runs ip_name_synth_1]

launch_runs synth_1

wait_on_run synth_1

launch_runs impl_1

 

For non-project mode

 

read_ip ip_name.xci

generate_target all [get_ips ip_name]
synth_ip [get_ips ip_name]

synth_design

opt_design

 

Thanks,

Deepika.

Thanks,
Deepika.
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Moderator
Moderator
19,655 Views
Registered: ‎01-16-2013

@arnold80,

 

Seems to be some issue with the TCL command used as it is working in Project flow.

Since it is working when you click on Run Implementation. check the exact command in .jou or runme.log file which is getting applied for opt_design.

 

Regards,

Syed

 

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Highlighted
Xilinx Employee
Xilinx Employee
35,974 Views
Registered: ‎09-20-2012

Hi @arnold80

 

Are you using project mode or non-project mode when running using TCL?

 

It looks like you are combining the project mode and non project mode commands.

 

If you want to use project mode then use the below commands

 

add_files ip_name.xci or import_files

generate_target all [get_ips ip_name]

create_ip_run [get_ips ip_name]

launch_runs [get_runs ip_name_synth_1]

launch_runs synth_1

wait_on_run synth_1

launch_runs impl_1

 

For non-project mode

 

read_ip ip_name.xci

generate_target all [get_ips ip_name]
synth_ip [get_ips ip_name]

synth_design

opt_design

 

Thanks,

Deepika.

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)

View solution in original post

Highlighted
Visitor
Visitor
19,598 Views
Registered: ‎02-10-2016

Thank you for your replies. The mix and match of project vs non-project mode functions was indeed an issue, my intention was to use project mode. Another issue was, as you pointed out, that I never ran create_ip_run / synth_ip. That is what caused the error message. Anyhow, the problem is solved now thanks to your swift support.

 

Thanks,

Arnold

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Visitor
Visitor
13,758 Views
Registered: ‎08-31-2016

Hi I'm seeing a similar issue but the error is associated with a microblaze_mcs

I created a qdr-iv IP that im using in my design and i'm able to synthesize the ip but can't implement the design. I get an error message saying: 

ERROR: [DRC 23-20] Rule violation (INBB-3) Black Box Instances - Cell 'sram_interface_inst/raw_qdr4_sram_interface_inst/qdriv_inst/cal/u_cal_riu/mcs0' of type 'sram_interface_inst/raw_qdr4_sram_interface_inst/qdriv_inst/cal/u_cal_riu/mcs0/microblaze_mcs' has undefined contents and is considered a black box. The contents of this cell must be defined for opt_design to complete successfully.

 

I'm using a TCL script to import the files for the ip by:

read_ip [list ${VHDL_DIR}/coregen/qdriv_1/qdriv_1.xci]
generate_target all [get_ips ${VHDL_DIR}/coregen/qdriv_1/qdriv_1]
synth_ip [get_ips ${VHDL_DIR}/coregen/qdriv_1/qdriv_1]

 

Any ideas what I'm missing?

 

Thanks

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