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Explorer
Explorer
8,341 Views
Registered: ‎09-16-2013

ERROR:Place:1377 - Regional clock net

Hi all,

 

 

I am getting the below error, please let me know the solution.

Tool: ISE 14.6

Device: virtex 6

 

 

ERROR:Place:1377 - Regional clock net
   "u_ddr3/u_memc_ui_top/u_mem_intfc/phy_top0/clk_rsync<0>" is not routable with
   loads locked in different clock regions such that it will be impossible for
   the source to be routed to all loads. See below for a list of sample locked
   components in each clock region. For more information on the clock region
   rules, please refer to the architecture user's guide. To debug your design
   with partially routed design, please allow mapper/placer to finish the
   execution (by setting environment variable XIL_PAR_DEBUG_IOCLKPLACER to 1).
   
ERROR:Place:1377 - Regional clock net
   "u_ddr3/u_memc_ui_top/u_mem_intfc/phy_top0/clk_rsync<0>" is not routable with
   loads locked in different clock regions such that it will be impossible for
   the source to be routed to all loads. See below for a list of sample locked
   components in each clock region. For more information on the clock region
   rules, please refer to the architecture user's guide. To debug your design
   with partially routed design, please allow mapper/placer to finish the
   execution (by setting environment variable XIL_PAR_DEBUG_IOCLKPLACER to 1).
  

Thanks
Naveen G K
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5 Replies
Moderator
Moderator
8,338 Views
Registered: ‎06-24-2015

Re: ERROR:Place:1377 - Regional clock net

Hi @naveengk14,

 

At best a regional clock buffer (BUFR) can only reach loads in the same or vertically adjacent clock region. If the loads are constrained elsewhere you will see this error. To debug, set the variable and then examine the resulting unroutable NCD in FPGA Editor to determine which loads are causing the problem. Examine the constraints for those loads.

 

Thanks,
Nupur
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Xilinx Employee
Xilinx Employee
8,334 Views
Registered: ‎09-20-2012

Re: ERROR:Place:1377 - Regional clock net

Hi @naveengk14

 

Are you using MIG IP?

 

In case if you have modified the MIG IO pinout after MIG IP generation then use "verify UCF and update design" option in MIG and regenerate MIG RTL for new MIG UCF.

Thanks,
Deepika.
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Xilinx Employee
Xilinx Employee
8,089 Views
Registered: ‎09-20-2012

Re: ERROR:Place:1377 - Regional clock net

Hi @naveengk14

 

Did you try the suggestions from earlier posts?

Thanks,
Deepika.
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Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)
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Newbie liwengang
Newbie
543 Views
Registered: ‎09-19-2018

Re: ERROR:Place:1377 - Regional clock net

hi,

    I have met the same question, but a little different. in the example design, I used the ucf which recommended by MIG and no error occured. but after i added  other user logic , this error occured. so ,what can i do?

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Xilinx Employee
Xilinx Employee
514 Views
Registered: ‎05-08-2012

Re: ERROR:Place:1377 - Regional clock net

Hi @liwengang. Since this is a new issue, can you enter a new post, and indicate what type of buffer is driving the loads in question?

 


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