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11,839 Views
Registered: ‎12-04-2013

ERROR: [Place 30-660] Global clock spines are oversubscribed.

I ran into an error described here: http://forums.xilinx.com/t5/Implementation/error-of-Sub-optimal-placement-for-an-MMCM-BUFG-component-pair/td-p/387293. After I constrained set_property CLOCK_DEDICATED_ROUTE FALSE it ran into the error ERROR: [Place 30-660] Global clock spines are oversubscribed. The following clock nets need to use global clock spine 1 in SLR 0: <net1> and <net2>

 

There were 4 WARNINGs before this error:

WARNING: [Place 30-495] Global clock spine 0 is shared by 2 clock buffers. This may have a negative effect on QOR as the loads of these clocks have to be constrained to specific SLRs. The following buffers are using this spine...

 

How do I resolve this error?

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Xilinx Employee
Xilinx Employee
11,819 Views
Registered: ‎08-02-2007

Re: ERROR: [Place 30-660] Global clock spines are oversubscribed.

Hi,

 

In V7 2000T device, there are 32 BUFG’s per SLR. There are some limitations on the placement of these buffers.

 

A single global clock buffer can drive any clocking point in any SLR. The global clock buffers are competing for the 32 available interposer clock backbone tracks. A track driven by a BUFG in one SLR cannot be driven by another BUFG in the same or any other SLR.

 

Because each SLR clock track is segmentable at the SLR boundary, a BUFG in one SLR can use the same track as a BUFG in an adjacent SLR as long as the clocking is local to the SLR and does not need to connect to an adjacent SLR.

 

For example, in the largest SSI device (XC7V2000T), each of the SLRs has 32 BUFGs. The BUFGs and the associated clock nets can be viewed as four groups of 0–31, 32–63, 64–95, and 96–127 from the bottom SLR up to the top. BUFGs and clock nets that are multiples of 32 (32 indices apart from each other) contend for the same interposer backbone resources. In this XC7V2000T example, these are SLR clock nets 0, 32, 64, and 96; 1, 33, 65, and 97; and so on. With four SLRs, the BUFGs X0Y0, X0Y32, X0Y64, and X0Y96  connect to the same track 0 in the interposer backbone. Therefore, only one of those buffers can be used in the design. Similarly, the BUFGs X0Y1, X0Y33, X0Y65, and X0Y97 (all BUFG1s) compete for interposer backbone track 1.

 

This error can be fixed by locking the BUFG's in error to sites which are not multiples of 32.

 

--HS

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Highlighted
11,807 Views
Registered: ‎12-04-2013

Re: ERROR: [Place 30-660] Global clock spines are oversubscribed.

Hi,

 

Thanks for the explanation.

I am new to this. Is there a guide where I can see how to constrain the clock buffers?

Placement for BUFGs etc?

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Xilinx Employee
Xilinx Employee
11,800 Views
Registered: ‎09-20-2012

Re: ERROR: [Place 30-660] Global clock spines are oversubscribed.

Hi,

Open synthesized design and search for the nets with names given in error message. Get the instance names of bufgs connected to these nets and write below constraints in XDC.

set_property LOC BUFGCTRL_XxYy [get_cells bufg_instance_name]

In this way write two constraints and lock the bufg's to sites which are not multiples of 32.

Thanks,
Deepika.
Thanks,
Deepika.
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11,792 Views
Registered: ‎12-04-2013

Re: ERROR: [Place 30-660] Global clock spines are oversubscribed.

Thanks,

 

Is there anyway to constrain the BUFG just to 1 side of the device like X1 or X0?

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Xilinx Employee
Xilinx Employee
11,782 Views
Registered: ‎09-20-2012

Re: ERROR: [Place 30-660] Global clock spines are oversubscribed.

Hi,

 

You can give a range of values like below

 

create_pblock test
add_cells_to_pblock test [get_cells {bufg_inst_name}] -clear_locs
resize_pblock test -add {BUFGCTRL_X0Y0:BUFGCTRL_X0Y31}

 

Thanks,

Deepika.

 

Thanks,
Deepika.
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11,774 Views
Registered: ‎12-04-2013

Re: ERROR: [Place 30-660] Global clock spines are oversubscribed.

Thanks,

 

Can you also please give me a syntax to the problem mentioned here : http://forums.xilinx.com/t5/Implementation/error-of-Sub-optimal-placement-for-an-MMCM-BUFG-component....

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Xilinx Employee
Xilinx Employee
11,767 Views
Registered: ‎09-20-2012

Re: ERROR: [Place 30-660] Global clock spines are oversubscribed.

Hi,

 

It is not recommended to use CLOCK_DEDICATED_ROUTE = FALSE constraint as this affects timing badly.

 

You can try locking the MMCM and BUFG to same half of device as suggested in the other thread. Assuming you are using vivado, the constraints looks like below

 

set_property LOC BUFGCTRL_XxYy [get_cells bufg_name]

set_property LOC MMCME2_ADV_XxYy [get_cells mmcm_name]

 

You can search for the sites in device view of synthesized design and check which sites of MMCM and BUFG are in same half of device. Later you can use those site names in the above constraints.

 

Thanks,

Deepika.

Thanks,
Deepika.
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Visitor
Visitor
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Registered: ‎12-17-2009

Re: ERROR: [Place 30-660] Global clock spines are oversubscribed.

I'm running into this same issue myself.

 

Is there some reason why the vivado  placer can't resolve this conflict itself by moving the placement of the BUFGs around?  I have < 25 clocks or nets using BUFG's, so if there is 32 global clock splines per SLR, why can't the placer figure that out??

 

 

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Historian
Historian
11,585 Views
Registered: ‎02-25-2008

Re: ERROR: [Place 30-660] Global clock spines are oversubscribed.


@davemac22 wrote:

I'm running into this same issue myself.

 

Is there some reason why the vivado  placer can't resolve this conflict itself by moving the placement of the BUFGs around?  I have < 25 clocks or nets using BUFG's, so if there is 32 global clock splines per SLR, why can't the placer figure that out?? 


ISE could never figure it out, either, so why would one expect the newest, written-from-the-ground-up tool to figure it out?

----------------------------Yes, I do this for a living.
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Visitor
Visitor
5,803 Views
Registered: ‎12-17-2009

Re: ERROR: [Place 30-660] Global clock spines are oversubscribed.

Well it ain't rocket science, or is it?  lol. :)

 

Actually I'm wondering if maybe the placer is smart enough to take care of this and what is happening in my case is that the global clock splines are being used to connect some of my MMCM outputs to my complex BUFGMUX network? (ie. some of my MMCM clk outputs have to drive more than one BUFG).  In that case, I may be just over the limit.

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Scholar
Scholar
1,303 Views
Registered: ‎08-14-2007

Re: ERROR: [Place 30-660] Global clock spines are oversubscribed.

Hi 

It was a specific solution for this issue?

 

 

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