ERROR: [Place 30-675] Sub-optimal placement for a global clock-capable IO pin and BUFG pair.

[niwis]

Hello,

during implementation the error mentioned in the subject occured. I followed the steps described here and locked the BUFG to the same clock region as the I/O port. However, the same error still persists and a few more errors came up. The complete output of the corresponding section can be seen below.

The strange part is that BUFGCE_HDIO_X1Y9 is in the same clock region as IOB_X0Y276, so I really don't know what the issue is. Does anyone know why does the error persists?

Thank you!

Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
CRITICAL WARNING: [Place 30-73] Invalid constraint on register 'ps_har_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/IO1_I_REG'. It has the property IOB=TRUE, but it is not driving or driven by any IO element.
WARNING: [Place 30-568] A LUT 'ps_har_i/har_wrap_0/inst/har_top_i/peripherals_i/apb_trng_i/i_NDRNG/i_clock_gating_cell/ngnvwhzo4[15]_i_3' is driving clock pin of 1128 registers. This could lead to large hold time violations. First few involved registers are:
	ps_har_i/har_wrap_0/inst/har_top_i/peripherals_i/apb_trng_i/i_NDRNG/i_test_health/i_test_proportion/NbDet_reg[4] {FDCE}
	ps_har_i/har_wrap_0/inst/har_top_i/peripherals_i/apb_trng_i/i_NDRNG/i_test_health/i_test_proportion/nvb7jkvn3_reg[8] {FDPE}
	ps_har_i/har_wrap_0/inst/har_top_i/peripherals_i/apb_trng_i/i_NDRNG/i_test_health/BitCnt_reg[3] {FDCE}
	ps_har_i/har_wrap_0/inst/har_top_i/peripherals_i/apb_trng_i/i_NDRNG/i_test_health/i_test_proportion/nvb7jkvn3_reg[7] {FDPE}
	ps_har_i/har_wrap_0/inst/har_top_i/peripherals_i/apb_trng_i/i_NDRNG/i_test_health/BitCnt_reg[1] {FDCE}
INFO: [Timing 38-35] Done setting XDC timing constraints.
ERROR: [Place 30-68] Instance ps_har_i/har_wrap_0/inst/clk_rst_gen_i/clock_gen_i/inst/clkin1_bufg (BUFGCE) is not placed
ERROR: [Place 30-68] Instance ps_har_i/har_wrap_0/inst/clk_rst_gen_i/clock_gen_i/inst/clkout1_buf (BUFGCE) is not placed
ERROR: [Place 30-68] Instance ps_har_i/har_wrap_0/inst/clk_rst_gen_i/clock_gen_i/inst/mmcme4_adv_inst (MMCME4_ADV) is not placed
ERROR: [Place 30-68] Instance ps_har_i/har_wrap_0/inst/har_top_i/axi_spi_slave_i/axi_spi_slave_i/u_txreg/BUFGMUX_inst (BUFGCTRL) is not placed
ERROR: [Place 30-68] Instance ps_har_i/util_ds_buf_0/U0/USE_BUFG.GEN_BUFG[0].BUFG_U (BUFGCE) is not placed
ERROR: [Place 30-68] Instance ps_har_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG (BUFG_PS) is not placed
ERROR: [Place 30-675] Sub-optimal placement for a global clock-capable IO pin and BUFG pair.If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
	< set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets tck_i_IBUF_inst/O] >

	tck_i_IBUF_inst/IBUFCTRL_INST (IBUFCTRL.O) is locked to IOB_X0Y276
	ps_har_i/util_ds_buf_0/U0/USE_BUFG.GEN_BUFG[0].BUFG_U (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_HDIO_X1Y9

	The above error could possibly be related to other connected instances. Following is a list of 
	all the related clock rules and their respective instances.

	Clock Rule: rule_bufg_clockregion_prop
	Status: PASS 
	Rule Description: A global clock source buffer with CLOCK_REGION property should get placed in the
	clock region specified by the property
	ps_har_i/util_ds_buf_0/U0/USE_BUFG.GEN_BUFG[0].BUFG_U (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_HDIO_X1Y9

	Clock Rule: rule_bufgce_bufg_conflict
	Status: PASS 
	Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be
	used at the same time
	ps_har_i/util_ds_buf_0/U0/USE_BUFG.GEN_BUFG[0].BUFG_U (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_HDIO_X1Y9

Resolution: A dedicated routing path between the two can be used if: (a) The global clock-capable IO (GCIO) is placed on a GCIO capable site (b) The BUFG is placed in the same bank of the device as the GCIO pin. Both the above conditions must be met at the same time, else it may lead to longer and less predictable clock insertion delays.
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: b72d0a30

Time (s): cpu = 00:01:18 ; elapsed = 00:00:30 . Memory (MB): peak = 5505.266 ; gain = 0.000 ; free physical = 7457 ; free virtual = 12138
Phase 1 Placer Initialization | Checksum: b72d0a30

Time (s): cpu = 00:01:18 ; elapsed = 00:00:30 . Memory (MB): peak = 5505.266 ; gain = 0.000 ; free physical = 7457 ; free virtual = 12138
ERROR: [Place 30-99] Placer failed with error: 'IO Clock Placer failed'
Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure.

[rshekhaw]

Hi @niwis ,

Have you checked this AR#,If not please have a look:

https://www.xilinx.com/support/answers/66659.html

Thanks,

Raj

[niwis]

Hello @rshekhaw ,

this is the page I refered to in my original post. So yes, I followed the steps described there and fixed the clock region for the BUFG, and the result is the output given in the OP

[marcb]

Hi @niwis 

Which Vivado version is this?

You should be able to overcome this with either a LOC constraint, or a CLOCK_REGION constraint.

set_property LOC BUFGCE_HDIO_X*Y* [get_cells ...]

or 

set_property CLOCK_REGION <clock_region_value> [get_cells ...]

If a reproducible DCP is available, this can be checked to see if there is an issue to report to development.

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------