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Voyager
Voyager
341 Views
Registered: ‎04-11-2016

ERROR: [Route 35-368] Router failed to resolve global congestion

Hi,

I am using vu440 for a design which has resource utilization of about 74% LUTs but I run into congestion issue:

ERROR: [Route 35-368] Router failed to resolve global congestion
Phase 3.1.2 Run Global Routing | Checksum: ae73779c

Time (s): cpu = 04:12:35 ; elapsed = 02:17:59 . Memory (MB): peak = 44210.004 ; gain = 0.000 ; free physical = 325191 ; free virtual = 735377
Phase 3.1 Global Routing | Checksum: 1aa733af3

Time (s): cpu = 04:12:41 ; elapsed = 02:18:05 . Memory (MB): peak = 44210.004 ; gain = 0.000 ; free physical = 327893 ; free virtual = 738079
Phase 3 Initial Routing | Checksum: 1aa733af3

Time (s): cpu = 04:12:45 ; elapsed = 02:18:09 . Memory (MB): peak = 44210.004 ; gain = 0.000 ; free physical = 327893 ; free virtual = 738079

Router Utilization Summary
  Global Vertical Routing Utilization    = 0 %
  Global Horizontal Routing Utilization  = 0 %
  Routable Net Status*
  *Does not include unroutable nets such as driverless and loadless.
  Run report_route_status for detailed report.
  Number of Failed Nets               = 4111280
  Number of Unrouted Nets             = 3541743
  Number of Partially Routed Nets     = 569537
  Number of Node Overlaps             = 0

Congestion Report
North Dir 1x1 Area, Max Cong = 0%, No Congested Regions.
South Dir 1x1 Area, Max Cong = 0%, No Congested Regions.
East Dir 1x1 Area, Max Cong = 0%, No Congested Regions.
West Dir 1x1 Area, Max Cong = 0%, No Congested Regions.

------------------------------
Reporting congestion hotspots
------------------------------
Direction: North
----------------
Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
Direction: South
----------------
Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
Direction: East
----------------
Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
Direction: West
----------------
Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0

INFO: [Route 35-17] Router encountered errors. Please check the log file for details

Time (s): cpu = 04:13:30 ; elapsed = 02:18:29 . Memory (MB): peak = 44210.004 ; gain = 0.000 ; free physical = 335156 ; free virtual = 745343
INFO: [Common 17-83] Releasing license: Implementation
7 Infos, 0 Warnings, 0 Critical Warnings and 1 Errors encountered.
route_design failed
route_design: Time (s): cpu = 04:19:53 ; elapsed = 02:24:46 . Memory (MB): peak = 44210.004 ; gain = 0.000 ; free physical = 335156 ; free virtual = 745343
ERROR: [Common 17-39] 'route_design' failed due to earlier errors.

    while executing
"route_design -directive AlternateCLBRouting"
    ("eval" body line 1)
    invoked from within
"eval route_design $route_design_flags"
    (file "/..." line 315)
INFO: [Common 17-206] Exiting Vivado at Tue May 26 01:54:04 2020...

report_qor_suggestions   show me:

2. QoR Suggestions - Congestion
-------------------------------

2.1 Summary
-----------

+---------------------+---------------------+------------------------------+-----------------------------------+
|      Suggestion     |     Description     |           Next Step          |            Explanation            |
+---------------------+---------------------+------------------------------+-----------------------------------+
| CONG-31             | Congestion in the   | Run "opt_design              | Design has congestion, So using   |
|                     | design              | -merge_equivalent_drivers"   | opt_design                        |
|                     |                     |                              | -merge_equivalent_drivers will    |
|                     |                     |                              | save some area and improve        |
|                     |                     |                              | congestion.                       |
| CONG-3              | Congestion due to   | Rerun with -output_dir to    | Found high levels of LUT          |
|                     | LUT combining       | generate the TCL & XDC       | combining within congested        |
|                     |                     | files. Run "read_xdc         | regions. Disabling LUT combining  |
|                     |                     | RQSPreSynth.xdc" or "source  | for logic within congested        |
|                     |                     | RQSPreImpl.tcl"              | regions can reduce congestion.    |
| CONG-5              | Congestion due to   | Rerun with -output_dir to    | Found high LUTRAM utilization     |
|                     | high LUTRAM usage   | generate the TCL file. Run   | within congested regions. Mapping |
|                     |                     | "source RQSImplCommon.tcl"   | memory within congested regions   |
|                     |                     | and "place_design"           | to BRAM instead of LUTRAM cells   |
|                     |                     |                              | can reduce congestion.            |
+---------------------+---------------------+------------------------------+-----------------------------------+

 

2.2 Details
-----------

+------------+-------+------+-------------+--------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------+
| Suggestion | Level | Type |  Direction  |                Window                |                                                                                                     Congested Modules                                                                                                     | High Fanout |
+------------+-------+------+-------------+--------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------+
| CONG-3     |     8 |      | North       | (CLEL_R_X25Y381,CLE_M_X153Y636)      | I_          | NA          |
|            |     8 |      | East        | (CLEL_R_X52Y602,CLEL_R_X179Y857)     | I_   | NA          |
|            |     8 |      | South       | (CLEL_R_X49Y106,CLEL_R_X176Y361)     | I_                                                         | NA          |
|            |     8 |      | West        | (LAGUNA_TILE_X16Y33,CLEL_R_X143Y288) | I_               | NA          |
|            |     6 |      | East_Short  | (CLEL_R_X131Y738,CLEL_R_X162Y801)    | I_ | NA          |
|            |     6 |      | West_Short  | (CLEL_L_X73Y383,CLEL_R_X104Y446)     | I_               | NA          |
|            |     5 |      | South_Short | (CLEL_L_X126Y459,CLEL_R_X141Y490)    | I_            | NA          |
| CONG-5     |     8 |      | North       | (CLEL_R_X25Y381,CLE_M_X153Y636)      | I_                                                                                                                                                        | NA          |
|            |     8 |      | East        | (CLEL_R_X52Y602,CLEL_R_X179Y857)     | I_                                                                                                                                                   | NA          |
|            |     8 |      | South       | (CLEL_R_X49Y106,CLEL_R_X176Y361)     | I_                                                                                                                                                        | NA          |
|            |     8 |      | West        | (LAGUNA_TILE_X16Y33,CLEL_R_X143Y288) | I_                                                                                                                                                        | NA          |
|            |     6 |      | East_Short  | (CLEL_R_X131Y738,CLEL_R_X162Y801)    | I_                                                                                                                                                   | NA          |
|            |     6 |      | West_Short  | (CLEL_L_X73Y383,CLEL_R_X104Y446)     | I_                                                                                                                                                       | NA          |
|            |     5 |      | South_Short | (CLEL_L_X126Y459,CLEL_R_X141Y490)    | I_                                                                                                                                                        | NA          |
+------------+-------+------+-------------+--------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------+

The suggestion "map memory to BRAM instead of LUTRAM" is not possible because BRAM creates an extra delay which is not the requirement of the design.

I tried to use several strategies in synthesis like:

 -no_lc  -resource_sharing off -keep_equivalent_registers -retiming -fanout_limit 100

but it didn't help.

The measure problem is with LUT combination. When I use -no lc strategy in synthesis the resource utilization jumps from 74% to 106%. i.e. it creates resource problem.

In opt and placement I tried also several strategies like:

opt_design -directive Explore

place_design -no_bufg_opt -directive AltSpreadLogic_high

place_design -no_bufg_opt -directive SSI_SpreadLogic_high

phys_opt_design -directive AggresiveExplore

but it didn't help.

Any suggestion for such situation?

 

 

 

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Xilinx Employee
Xilinx Employee
331 Views
Registered: ‎05-22-2018

Re: ERROR: [Route 35-368] Router failed to resolve global congestion

Hi @fpgalearner ,

Which Vivado version you are working with? 2019.1/2

Then please run RQS flow on that, for delatiled information on that please check the below blog:

https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/Improving-QoR-with-report-qor-suggestions-in-Vivado/ba-p/1033308

Also parallelly if possible please share the post place dcp file with us.

If you are ok with that let me know i will share the secure EZMove package link.

Thanks,

Raj.

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Moderator
Moderator
315 Views
Registered: ‎01-16-2013

Re: ERROR: [Route 35-368] Router failed to resolve global congestion

@fpgalearner 

 

Check "Addressing Congestion" topic in below user guide:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_2/ug949-vivado-design-methodology.pdf#page=258 

Disable lut combining on page 263 might be helpful in your case. If you can share the dcp file as suggested above then we can have a look. 

 

--SYed

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Did you check our new quick reference timing closure guide (UG1292)?
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Voyager
Voyager
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Registered: ‎04-11-2016

Re: ERROR: [Route 35-368] Router failed to resolve global congestion

@rshekhaw @syedz 

I am using vivado/2018.2.

I have already posted the report of QOR suggestion in original post. write and read QOR not tested yet. will let you know. As I mentioned above, switching off (- no lc) LUT combination leads to 106% resource need.

Unfortunately I can not share the dcp(design) here. We have Xilinx FAE. In case it not solved here then I have to go through him.

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Voyager
Voyager
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Registered: ‎06-20-2012

Re: ERROR: [Route 35-368] Router failed to resolve global congestion

Hi @fpgalearner 

Try to help the router with an initial floorplan based on pblocks.

== If this was helpful, please feel free to give Kudos, and close if it answers your question ==
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Voyager
Voyager
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Registered: ‎04-11-2016

Re: ERROR: [Route 35-368] Router failed to resolve global congestion

@rshekhaw @syedz @calibra 

This is just message info or does it also have any impact on Vivado P&R?

INFO: [Common 17-14] Message 'Physopt 32-81' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.

I saw Xilinx AR about this:

https://www.xilinx.com/support/answers/53034.html

My design is compiling since 29 hrs and at this position it is since 6 hrs and seems like got stuck at this point.

Any clue what can be done?

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Moderator
Moderator
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Registered: ‎01-16-2013

Re: ERROR: [Route 35-368] Router failed to resolve global congestion

@fpgalearner 

 

Since this is at physopt, I think the tool is most likely trying to fix timing or reducing congestion by optimization.

Did you check post place timing WNS and if it an acceptable number. We have this very short sheet which captures/addresses very good points in timing closure. Please check once:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_2/ug1292-ultrafast-timing-closure-quick-reference.pdf 

 

For resolving congestion, I start debugging from following report:

report_design_analysis, report_utilization, report_high_fanout_nets & xilinx::designutils::report_failfast

 

--Syed

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Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

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Voyager
Voyager
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Registered: ‎04-11-2016

Re: ERROR: [Route 35-368] Router failed to resolve global congestion

@syedz 

I have an out of context synthesized submodule in the design added as dcp and I added constraints for the clock used in this submodule in the topmodule from where it gets instantiated.

When I was writing checkpoint dcp for this submodule, there was following warning which I ignored:

WARNING: [Constraints 18-5210] No constraint will be written out.

Now when I try to run the command you mentioned "report_design_analysis" , in that submodule  there is a warning concerning clock:

WARNING: [Timing 38-242] The property HD.CLK_SRC of clock port "clk" is not set. In out-of-context mode, this prevents timing estimation for clock delay/skew
Resolution: Set the HD.CLK_SRC property of the out-of-context port to the location of the clock buffer instance in the top-level design

Does it mean dcp file which had no constrained added during its generation creates problem in design? I mean it taking too long. DO I need to add this directly in the submodule generation?

 

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