10-05-2016 02:32 AM
I have a MIG (ddr4) in the design and Using Viavado 2016.2
After sy7nthesis I get the fopllowing error
ERROR: [Vivado_Tcl 4-414] Found memory core that needs to be (re) generated. Please run opt_design or implement_mig_core prior to launch place_design.
I followed as suggested (open synthesized design, implement_mig_core, implement_debug_core, save constraints, and place_design )
I get the same error again.
I also regenerated mig many times.
Please suggest. Thanks.
10-05-2016 07:36 AM
Are you using Vivado GUI or using TCL script to run the design?
Is the DDR4 IP generated in same version of vivado?
10-19-2016 08:19 PM
10-21-2016 03:48 AM
Are you adding XDF file to project?
03-31-2017 01:45 AM
03-31-2017 03:58 AM
One should not be disabling opt_design stage. This is mandatory step as it performs necessary optimizations and generates optimal netlist for placement.
Also Ultrascale MIG PHY gets generated during this stage, if you skip this stage you may run in to errors like this.