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verylsi
Visitor
Visitor
7,383 Views
Registered: ‎10-04-2016

ERROR: [Vivado_Tcl 4-414] Found memory core that needs to be (re) generated.

I have a MIG (ddr4) in the design and Using Viavado 2016.2 

After sy7nthesis I get the fopllowing  error 

ERROR: [Vivado_Tcl 4-414] Found memory core that needs to be (re) generated. Please run opt_design  or implement_mig_core prior to launch place_design.

 

I followed as suggested (open synthesized design,  implement_mig_core, implement_debug_core, save constraints, and place_design )

 

I get the same error again.

 

I also regenerated mig many times.

Please suggest. Thanks.

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7 Replies
vemulad
Xilinx Employee
Xilinx Employee
7,365 Views
Registered: ‎09-20-2012

Hi @verylsi

 

Are you using Vivado GUI or using TCL script to run the design?

 

Is the DDR4 IP generated in same version of vivado?

 

Thanks,
Deepika.
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verylsi
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7,178 Views
Registered: ‎10-04-2016

Hello Deepika,

Sorry for delayed response .
I am using vivado 2016.2 gui
and implement_mig_core, implement_debug_core, save constraints, and place_design commands are given in the tcl console.
I am generating memory cores from vivado 2016.2 but i am using xdf file of example design of vivado 2015. can that be a problem ?
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vemulad
Xilinx Employee
Xilinx Employee
7,147 Views
Registered: ‎09-20-2012

Hi @verylsi

 

Are you adding XDF file to project?

Thanks,
Deepika.
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xiaohu125
Contributor
Contributor
5,520 Views
Registered: ‎06-13-2014

Hi, @vemulad

 

I got the same issue. 

I am using Vivado GUI 2016.2 and I re-generate all ip core of my design in 2016.2.

 

How to resolve it?

 

Thank you

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xiaohu125
Contributor
Contributor
5,517 Views
Registered: ‎06-13-2014

After I enable opt_design option in design run settings window, the error id solved.
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vemulad
Xilinx Employee
Xilinx Employee
5,507 Views
Registered: ‎09-20-2012

Hi @xiaohu125

 

One should not be disabling opt_design stage. This is mandatory step as it performs necessary optimizations and generates optimal netlist for placement.

 

Also Ultrascale MIG PHY gets generated during this stage, if you skip this stage you may run in to errors like this.

Thanks,
Deepika.
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xiaohu125
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5,491 Views
Registered: ‎06-13-2014

Hi, @vemulad

 

Thank you for your quick and great reply.

 

Regards,

Xiaohu125

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