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Observer yangf3
Observer
6,376 Views
Registered: ‎12-20-2007

Error: Design cannot be automatically placed

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I received a working design in schematics, and I translated it into verilog behavior models. The original design was implemented sucessfully. I used the same .ucf file but got an error with the new design.

 

ERROR:Place:207 - Due to SelectIO banking constraints, the IOBs in your design cannot be automatically placed.

 

346 signals are not completely routed.

WARNING:Par:100 - Design is not completely routed.

 

I used FPGA Editor to see all the unrouted nets. Many of them with names N# are not defined by me. I dont't know what they are, and there are too many nets to be routed manually. How can I solve this problem?

 

My ISE version is 8.1.03i. The target device is Spartan3 XC3S50. Thanks.

Message Edited by yangf3 on 02-04-2009 06:18 AM
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1 Solution

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Historian
Historian
7,425 Views
Registered: ‎02-25-2008

Re: Error: Design cannot be automatically placed

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yangf3 wrote:
Thanks for your reply. But I only used LVCMOS33, not a single LVCOMS25. The exactly same .ucf file works with the old design. Any other possible reasons? Thanks.

Are there any ports in the design that are NOT in the UCF?

 

I/Os default to LVCMOS25 unless otherwise changed in the UCF or in your code.

 

Do you have an differential pairs? There are a bunch of rules about diff pair placement.

 

-a

----------------------------Yes, I do this for a living.
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3 Replies
Historian
Historian
6,366 Views
Registered: ‎02-25-2008

Re: Error: Design cannot be automatically placed

Jump to solution

yangf3 wrote:

I received a working design in schematics, and I translated it into verilog behavior models. The original design was implemented sucessfully. I used the same .ucf file but got an error with the new design.

 

ERROR:Place:207 - Due to SelectIO banking constraints, the IOBs in your design cannot be automatically placed.

 

346 signals are not completely routed.

WARNING:Par:100 - Design is not completely routed.

 

I used FPGA Editor to see all the unrouted nets. Many of them with names N# are not defined by me. I dont't know what they are, and there are too many nets to be routed manually. How can I solve this problem?

 

My ISE version is 8.1.03i. The target device is Spartan3 XC3S50. Thanks.

Message Edited by yangf3 on 02-04-2009 06:18 AM

Forget the N# nets. Those are intermediates created by the synthesizer.

 

The real problem is explicitly stated in the error message. You probably have conflicting bank power-supply rails. Mixing ports with IOTYPE = LVCMOS33 and LVCMOS25 in the same bank will throw this error.

 

-a

----------------------------Yes, I do this for a living.
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Observer yangf3
Observer
6,363 Views
Registered: ‎12-20-2007

Re: Error: Design cannot be automatically placed

Jump to solution
Thanks for your reply. But I only used LVCMOS33, not a single LVCOMS25. The exactly same .ucf file works with the old design. Any other possible reasons? Thanks.
0 Kudos
Historian
Historian
7,426 Views
Registered: ‎02-25-2008

Re: Error: Design cannot be automatically placed

Jump to solution

yangf3 wrote:
Thanks for your reply. But I only used LVCMOS33, not a single LVCOMS25. The exactly same .ucf file works with the old design. Any other possible reasons? Thanks.

Are there any ports in the design that are NOT in the UCF?

 

I/Os default to LVCMOS25 unless otherwise changed in the UCF or in your code.

 

Do you have an differential pairs? There are a bunch of rules about diff pair placement.

 

-a

----------------------------Yes, I do this for a living.
0 Kudos