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Observer
Observer
1,524 Views
Registered: ‎09-27-2017

Error during Bitstream generator

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Hello,after syntesis and implementation runned successfully,I can't generate bitstream and Vivado 2017.1 give me this error,in attached file.Can be because I substitute present pll with another generate by wizard,due Vivado don't recognised it.My project start by a core downloaded on the net,made with Modelsim,so I think that there are 2 different standard.Someone can help me?

Err.png
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Observer
Observer
1,735 Views
Registered: ‎09-27-2017

I solved the problem simply saving the xdc file.I don't saved to make experiments.Now it work.

View solution in original post

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Scholar
Scholar
1,513 Views
Registered: ‎08-07-2014

@s96971,

 

Please read the messages carefully and try to understand what they are saying.They are well explained. Refer to the proper Vivado docu if you don't understand them.

 

From the SS, I see that your top-level ports are not assigned to any FPGA Pins [DRC UCIO-1]. Then the IO-STANDARD for these also needs to be specified [DRC NSTD-1], they cannot stay at "default".

 

Both the above info you can find from the board/device docu in the "Master Constraints File Listing" section.

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FPGA enthusiast!
All PMs will be ignored
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Moderator
Moderator
1,510 Views
Registered: ‎09-15-2016

Hi @s96971

 

As per errors you need to specify PACKAGE_PIN and IOSTANDARD for your top ports in the xdc. Refer this link below:

https://www.xilinx.com/support/answers/56354.html

 

Based on the FPGA family and theri parts, write appropriate physical constraints specifying  PACKAGE PIN and IOSTANDARD.

Refer below link for package pins for your FGPA device family.

https://www.xilinx.com/support/package-pinout-files.html

 

 

Regards
Rohit
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Observer
Observer
1,441 Views
Registered: ‎09-27-2017

Hello,thanks for fast answer.I forget to write that I'm new in this ambient,I haven't much experience.

I use Arty board,this https://reference.digilentinc.com/reference/programmable-logic/arty/start.

I searched pinout files as suggest me,but I can't find it.Mine is xc7a35ticsg324-1L,there is

xc735tcsg32, don't match.Finally I think that I find it here:

 

https://github.com/Digilent/Arty/blob/master/Resources/XDC/Arty_Master.xdc

 

Now I changed i/o std in schematic,find result. LVCMOS33 (all pins are this value),now ,how can I understand how put pins?

If I understand I must connect Arty pins with my design,for example,rxfifo_den is connect to  pin re on Arty etc.Is correct my think?

 

 

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Moderator
Moderator
1,430 Views
Registered: ‎01-16-2013

@s96971,

 

You need to define the IOSTANDARD and LOC constraint on the IO ports mentioned in error message.

 

--Syed

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Did you check our new quick reference timing closure guide (UG1292)?
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Observer
Observer
1,378 Views
Registered: ‎09-27-2017

Thanks Syed,the problem is that I don't surehow to do.

I tried to add new constraints,adding this at the project:

https://github.com/Digilent/Arty/blob/master/Resources/XDC/Arty_Master.xdc

Then,as indicate in this xdc,I uncomment the line that i want to change pin definition,for example rx_fifo_rden, in the (   ),after get_ports.but generating bistream the error continue to indicate 14 ports not defined,but I defined one,so the port not defined should be 13!What I wrong to do?

 

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Moderator
Moderator
1,338 Views
Registered: ‎05-08-2012

Hi @s96971. Can you attach the updated Arty_Master.xdc, and the Vivado log file which shows the UCIO-1 DRC? From a Vivado Project, the log file would be in the <project_name>.runs/impl_<#>/runme.log file. From this information, it can be identified if there is a syntax issue, or other problem.

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Observer
Observer
1,736 Views
Registered: ‎09-27-2017

I solved the problem simply saving the xdc file.I don't saved to make experiments.Now it work.

View solution in original post

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