04-18-2018 02:28 AM
Hello,after syntesis and implementation runned successfully,I can't generate bitstream and Vivado 2017.1 give me this error,in attached file.Can be because I substitute present pll with another generate by wizard,due Vivado don't recognised it.My project start by a core downloaded on the net,made with Modelsim,so I think that there are 2 different standard.Someone can help me?
04-18-2018 02:37 AM - edited 04-18-2018 02:38 AM
Please read the messages carefully and try to understand what they are saying.They are well explained. Refer to the proper Vivado docu if you don't understand them.
From the SS, I see that your top-level ports are not assigned to any FPGA Pins [DRC UCIO-1]. Then the IO-STANDARD for these also needs to be specified [DRC NSTD-1], they cannot stay at "default".
Both the above info you can find from the board/device docu in the "Master Constraints File Listing" section.
04-18-2018 02:39 AM - edited 04-18-2018 02:40 AM
As per errors you need to specify PACKAGE_PIN and IOSTANDARD for your top ports in the xdc. Refer this link below:
Based on the FPGA family and theri parts, write appropriate physical constraints specifying PACKAGE PIN and IOSTANDARD.
Refer below link for package pins for your FGPA device family.
04-23-2018 02:29 AM
Hello,thanks for fast answer.I forget to write that I'm new in this ambient,I haven't much experience.
I use Arty board,this https://reference.digilentinc.com/reference/programmable-logic/arty/start.
I searched pinout files as thakurr suggest me,but I can't find it.Mine is xc7a35ticsg324-1L,there is
xc735tcsg32, don't match.Finally I think that I find it here:
Now I changed i/o std in schematic,find result. LVCMOS33 (all pins are this value),now ,how can I understand how put pins?
If I understand I must connect Arty pins with my design,for example,rxfifo_den is connect to pin re on Arty etc.Is correct my think?
04-24-2018 04:08 AM
You need to define the IOSTANDARD and LOC constraint on the IO ports mentioned in error message.
04-30-2018 05:13 AM
Thanks Syed,the problem is that I don't surehow to do.
I tried to add new constraints,adding this at the project:
Then,as indicate in this xdc,I uncomment the line that i want to change pin definition,for example rx_fifo_rden, in the ( ),after get_ports.but generating bistream the error continue to indicate 14 ports not defined,but I defined one,so the port not defined should be 13!What I wrong to do?
04-30-2018 12:19 PM - edited 04-30-2018 12:20 PM
Hi @s96971. Can you attach the updated Arty_Master.xdc, and the Vivado log file which shows the UCIO-1 DRC? From a Vivado Project, the log file would be in the <project_name>.runs/impl_<#>/runme.log file. From this information, it can be identified if there is a syntax issue, or other problem.