12-01-2010 02:17 AM
I am using DDR2 component MT47J64M16
XX-3 with my microblaze processor. FPGA used is xc6lx150t-fg900
- 2. Now, what i did was, i tried to integrate the read and write of
this ddr2 with my FTDI USB. While compiling the whole code in ISE, I
got following error in map phase -
ERROR:Place - ConstraintResolved NO placeable site for
ERROR:Place - SIO has over-constrained componet
Inst_usb_edk/MCB_DDR2/MCB_DDR2/mpmc_core_0/gen_spartan6_mcb.gen_spartan6_bufpll_mcb.bufpll_0 to have to placeable
sites. Constraints come from driver constraints AND load IO constraints
ERROR:Pack:1654 - The timing-driven placement phase encountered an error
I am not getting with what this error is related to? and where should i look to resolve it?
12-01-2010 09:15 AM
I suggest that you examine the placement constraints on the components mentioned in the the messages.
02-08-2011 07:27 AM
I had the same problem and solved it changing the global clock input. It depends on the "bufp
ll_mcb.bufpll_0". Check your constraint for the global clock source in the system.ucf (in the mhs-File if used). Not every clock pin have the driving possibility. If you are not sure, start the MIG in the ISE and configure your design. The ucf generated from the ISE contains a valid information for the clock pins of your design.
02-22-2011 09:02 AM
Hi I'm desiging a system using a mpmc core and i also notice that when i changed the input BUFG primitive for IBUFG the same message as above started to happen . The map fails letting me know that it can find a placeable site .
If as the last message suggest .Not all the pins have the connecting possibility .But in my case this is my system clock .How can i connect it to the global network?
09-18-2012 04:48 AM
Thanks guys! You helped me to solve my problem as well. Changed IBUFG onto BUFG and it runs without errors now.