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Adventurer
Adventurer
1,212 Views
Registered: ‎09-18-2017

Error when manipulating AXI4 protocol VDMA-Axi Mem vivado 2017.4([Opt 31-67] Problem: A LUT3 cell in the design is missing a connection on input pin I0, which is used by the LUT equation)

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Hello!

 

I am trying to manipulate the AXI4 protocol by adding my own module in between a VDMA and axi4 mem interconnect peripheral.

However, when I try to “run the implementation” I get the following “famous” error.

lut3 problem.png

 

[Opt 31-67] Problem: A LUT3 cell in the design is missing a connection on input pin I0, which is used by the LUT equation. This pin has either been left unconnected in the design or the connection was removed due to the trimming of unused logic. The LUT cell name is: hdmi_i/axi_vdma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/I_WRESP_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN.data_reg[5][1]_srl6_i_1.

 

Clearly, the error is coming from the VDMA which is a Xilinx custom peripheral that can't be changed. Before this error occurred, I had problems with the Axi mem interconnect peripheral as well, namely problems pertaining to LUT2.

 

Luckily, by removing the fifo settings and setting it to none I could remove that error but the VDMA peripheral does not show any fifo options as the AXI interconnect(2.1).

 

 fifo settings.png

I have been seeing this problem on vivado 2017.3 and vivado 2017.4.

 

I am running this program as OOC in order to save time since I just want to code 1 module out of 20 modules in my design. Making a global run is taking a lot of time and we are short of time atm.

 

I have tried this https://www.xilinx.com/support/answers/70111.html and read other threads like https://forums.xilinx.com/t5/Implementation/ImplementationOpt-Design-Opt-31-67-Problem-for-AXI-bus-between/td-p/591319 but none of the solutions work for me right now.

 

My question to you is if it is possible to manipulate the AXI4 protocol by adding custom modules in between Xilinx peripherals?

 

I would be utterly grateful if I could get some suggestion regarding this error since it is a popular problem occurring on vivado 2017.4 although it was meant to be fixed.

 

I must make a timewise decision on whether it is worth to find ways to manipulate the AXI4 protocols by adding own modules. From what I have seen on this forum, many users are stuck on this error when they try to integrate their own module in between two Xilinx peripherals.

 

Regards,

 

John

 

 

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Adventurer
Adventurer
1,768 Views
Registered: ‎09-18-2017

Re: Error when manipulating AXI4 protocol VDMA-Axi Mem vivado 2017.4([Opt 31-67] Problem: A LUT3 cell in the design is missing a connection on input pin I0, which is used by the LUT equation)

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wohooo solved it thanks to my pHd friend :)

The problem is not with the tool.

 

Since optDesign is used to trim hardware logic it is trimming unused inputs and outputs from my RTL design thus removing connections that are not used but is available. My goal was to debug all the signals step by step but you cannot do that since you have to manipulate ALL your signals when you are in the implementation phase ( run implementation).

 

Every possible connection has to be manipulated when you run implementation. I double checked the log and saw that the bvalid signal was trimmed and would result in an error if not handled so I had to add extra logic and drive the output to 1 or 0 in my RTL design so that the compiler or optimizer oversees that the signal is used and thus cannot be trimmed. In my situation, this was a critical warning and not an error so the error I got was different but this was the issue. It is important to check the log since the critical warning was the main problem but I was stuck on another error that was hard to trace.

 

1. Every connection has to be validated and manipulated else the opt will trim it and remove connections.

2. Check the log for critical warnings since it clearly indicates which signals are the problem.

 

thanks for your response

6 Replies
Scholar markcurry
Scholar
1,191 Views
Registered: ‎09-16-2009

Re: Error when manipulating AXI4 protocol VDMA-Axi Mem vivado 2017.4([Opt 31-67] Problem: A LUT3 cell in the design is missing a connection on input pin I0, which is used by the LUT equation)

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John,

 

Is this an Error, or a Warning?

 

I recall similar messages from Vivado in the past.  When I opened a support ticket, it was determined that (whatever the root cause) the message could be ignored.  I don't recall at the moment whether or not I could just ignore it on my own (i.e. it was just a Warning), or I needed Xilinx help in moving forward. 

 

Regards,

 

Mark

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Adventurer
Adventurer
1,174 Views
Registered: ‎09-18-2017

Re: Error when manipulating AXI4 protocol VDMA-Axi Mem vivado 2017.4([Opt 31-67] Problem: A LUT3 cell in the design is missing a connection on input pin I0, which is used by the LUT equation)

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Hello @markcurry!

 

It is clearly an error which I have been trying to solve for several days but I am stuck. Again, by reading the related threads I see that the error always come up when a "custom module ( ex Johns_duplicatemodule) is put in between two Xilinx peripherals. 

 

As you can see the error cannot be removed by the user since I cannot enter or set any settings related to "data mover" when I double click on the VDMA module provided by Xilinx.

 

I might be wrong and would like to get help.

 

regards,

 

John

 

 

 

 

 

error.png

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Adventurer
Adventurer
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Registered: ‎09-18-2017

Re: Error when manipulating AXI4 protocol VDMA-Axi Mem vivado 2017.4([Opt 31-67] Problem: A LUT3 cell in the design is missing a connection on input pin I0, which is used by the LUT equation)

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PLUS+

 

Again, when running things globally, everything seems to work fine but taking a huge amount of time.

 

regards,

 

John

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Xilinx Employee
Xilinx Employee
1,159 Views
Registered: ‎08-02-2011

Re: Error when manipulating AXI4 protocol VDMA-Axi Mem vivado 2017.4([Opt 31-67] Problem: A LUT3 cell in the design is missing a connection on input pin I0, which is used by the LUT equation)

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Hi John,

The error is likely because something critical on the AXI interface is unconnected or improperly connected inside your custom block.

I would open up the synthesis design and try to find the offending cell then try to trace it back to a specific signal on the interface that is in question. This will help find a clue about where to trace it in the source code.

Can you post the RTL for the custom block, or is it sensitive?

What exactly is that custom block trying to do?
www.xilinx.com
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Adventurer
Adventurer
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Registered: ‎09-18-2017

Re: Error when manipulating AXI4 protocol VDMA-Axi Mem vivado 2017.4([Opt 31-67] Problem: A LUT3 cell in the design is missing a connection on input pin I0, which is used by the LUT equation)

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Hello Again!

 

I cannot share the RTL design here, but I am sure that the problem lies in the VDMA module.

 

I am going to manipulate the axi4 interface by duplicating writes and reads. For example write value X from VDMA in addres 40  , 30 and 235 in SDRAM(Although the VDMA instructs it to write to one specific place).

 

The problem is that I cannot change or dive into the VDMA module since it is a xlinix peripheral , the error comes from that peripheral which can clearly be seen from the error message on the implementation phase.

Check the marked text.

 

[Opt 31-67] Problem: A LUT3 cell in the design is missing a connection on input pin I0, which is used by the LUT equation. This pin has either been left unconnected in the design or the connection was removed due to the trimming of unused logic. The LUT cell name is:

hdmi_i/axi_vdma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/I_WRESP_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN.data_reg[5][1]_srl6_i_1.

 

The problem I see here is if it is even possible to manipulate axi4 peripherals since the user can just use the peripheral but not change it.

 

If this is not currenlty possible on vivado 2017.4 then I would be glad if you could confirm that since I dont really know if this works and so that i can stop this experiment and move on to my other project.

 

Just to remind I can run the whole block design globally but that gives me a compilation time of 25-35 minutes on a super computer which is very slow thus making it hard to debugg.

 

I have double checked the connections and I think the connections provided by the peripherals are connected correctly, I have also checked the RTL design the designs inside the VDMA is something I cannot change or connect since it is a Xlinix Peripheral.

 

I would be very glad if I could get any help. 

 

regards,

 

John

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Adventurer
Adventurer
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Registered: ‎09-18-2017

Re: Error when manipulating AXI4 protocol VDMA-Axi Mem vivado 2017.4([Opt 31-67] Problem: A LUT3 cell in the design is missing a connection on input pin I0, which is used by the LUT equation)

Jump to solution

wohooo solved it thanks to my pHd friend :)

The problem is not with the tool.

 

Since optDesign is used to trim hardware logic it is trimming unused inputs and outputs from my RTL design thus removing connections that are not used but is available. My goal was to debug all the signals step by step but you cannot do that since you have to manipulate ALL your signals when you are in the implementation phase ( run implementation).

 

Every possible connection has to be manipulated when you run implementation. I double checked the log and saw that the bvalid signal was trimmed and would result in an error if not handled so I had to add extra logic and drive the output to 1 or 0 in my RTL design so that the compiler or optimizer oversees that the signal is used and thus cannot be trimmed. In my situation, this was a critical warning and not an error so the error I got was different but this was the issue. It is important to check the log since the critical warning was the main problem but I was stuck on another error that was hard to trace.

 

1. Every connection has to be validated and manipulated else the opt will trim it and remove connections.

2. Check the log for critical warnings since it clearly indicates which signals are the problem.

 

thanks for your response