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Newbie pongowri07
Newbie
7,072 Views
Registered: ‎03-18-2014

Error while doing implement design

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity bmsu is
Port ( c,r,mad : in STD_LOGIC_VECTOR (7 downto 0);
clk,rst : in STD_LOGIC;
rr,cr : out STD_LOGIC_VECTOR (7 downto 0));
end bmsu;

architecture Behavioral of bmsu is

component crm is
Port ( c,r : in STD_LOGIC_VECTOR (7 downto 0);
crm_out : out STD_LOGIC_VECTOR (7 downto 0));
end component;

component comparator is
Port ( a,b : in STD_LOGIC_VECTOR (7 downto 0);
comp_out : out STD_LOGIC);
end component;

component and_gate is
Port ( a,b : in STD_LOGIC_VECTOR(7 DOWNTO 0);
en:STD_LOGIC;
rr,cr : out STD_LOGIC_VECTOR(7 DOWNTO 0));
end component;

component champ_reg is
Port ( reff_pix,crm_in : in STD_LOGIC_VECTOR (7 downto 0);
tr,rst : in STD_LOGIC;
rsr_out : out STD_LOGIC_VECTOR (7 downto 0));
end component;

signal comp_out:STD_LOGIC;
signal crm_out,champ_reg_out:STD_LOGIC_VECTOR (7 downto 0);
begin
crm_b:crm port map(c,r,crm_out);
champ_reg_b:champ_reg port map(mad,crm_out,clk,rst,champ_reg_out);
comp_b:comparator port map(mad,crm_out,comp_out);
and_g_b:and_gate port map(c,r,comp_out,rr,cr);


end Behavioral;

Reading design: bmsu.prj

=========================================================================
* HDL Compilation *
=========================================================================
Compiling vhdl file "C:/Xilinx91i/bmsu/bmsu.vhd" in Library work.
Architecture behavioral of Entity bmsu is up to date.

=========================================================================
* Design Hierarchy Analysis *
=========================================================================
Analyzing hierarchy for entity <bmsu> in library <work> (architecture <behavioral>).


=========================================================================
* HDL Analysis *
=========================================================================
Analyzing Entity <bmsu> in library <work> (Architecture <behavioral>).
WARNING:Xst:2211 - "C:/Xilinx91i/bmsu/bmsu.vhd" line 63: Instantiating black box module <crm>.
WARNING:Xst:2211 - "C:/Xilinx91i/bmsu/bmsu.vhd" line 64: Instantiating black box module <champ_reg>.
WARNING:Xst:2211 - "C:/Xilinx91i/bmsu/bmsu.vhd" line 65: Instantiating black box module <comparator>.
WARNING:Xst:2211 - "C:/Xilinx91i/bmsu/bmsu.vhd" line 66: Instantiating black box module <and_gate>.
Entity <bmsu> analyzed. Unit <bmsu> generated.


=========================================================================
* HDL Synthesis *
=========================================================================

Performing bidirectional port resolution...

Synthesizing Unit <bmsu>.
Related source file is "C:/Xilinx91i/bmsu/bmsu.vhd".
WARNING:Xst:646 - Signal <champ_reg_out> is assigned but never used.
Unit <bmsu> synthesized.


=========================================================================
HDL Synthesis Report

Found no macro
=========================================================================

=========================================================================
* Advanced HDL Synthesis *
=========================================================================

Loading device for application Rf_Device from file '3s250e.nph' in environment C:\Xilinx91i.

=========================================================================
Advanced HDL Synthesis Report

Found no macro
=========================================================================

=========================================================================
* Low Level Synthesis *
=========================================================================

Optimizing unit <bmsu> ...

Mapping all equations...
WARNING:Xst:2036 - Inserting OBUF on port <cr<7>> driven by black box <and_gate>. Possible simulation mismatch.
WARNING:Xst:2036 - Inserting OBUF on port <cr<6>> driven by black box <and_gate>. Possible simulation mismatch.
WARNING:Xst:2036 - Inserting OBUF on port <cr<5>> driven by black box <and_gate>. Possible simulation mismatch.
WARNING:Xst:2036 - Inserting OBUF on port <cr<4>> driven by black box <and_gate>. Possible simulation mismatch.
WARNING:Xst:2036 - Inserting OBUF on port <cr<3>> driven by black box <and_gate>. Possible simulation mismatch.
WARNING:Xst:2036 - Inserting OBUF on port <cr<2>> driven by black box <and_gate>. Possible simulation mismatch.
WARNING:Xst:2036 - Inserting OBUF on port <cr<1>> driven by black box <and_gate>. Possible simulation mismatch.
WARNING:Xst:2036 - Inserting OBUF on port <cr<0>> driven by black box <and_gate>. Possible simulation mismatch.
WARNING:Xst:2036 - Inserting OBUF on port <rr<7>> driven by black box <and_gate>. Possible simulation mismatch.
WARNING:Xst:2036 - Inserting OBUF on port <rr<6>> driven by black box <and_gate>. Possible simulation mismatch.
WARNING:Xst:2036 - Inserting OBUF on port <rr<5>> driven by black box <and_gate>. Possible simulation mismatch.
WARNING:Xst:2036 - Inserting OBUF on port <rr<4>> driven by black box <and_gate>. Possible simulation mismatch.
WARNING:Xst:2036 - Inserting OBUF on port <rr<3>> driven by black box <and_gate>. Possible simulation mismatch.
WARNING:Xst:2036 - Inserting OBUF on port <rr<2>> driven by black box <and_gate>. Possible simulation mismatch.
WARNING:Xst:2036 - Inserting OBUF on port <rr<1>> driven by black box <and_gate>. Possible simulation mismatch.
WARNING:Xst:2036 - Inserting OBUF on port <rr<0>> driven by black box <and_gate>. Possible simulation mismatch.
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block bmsu, actual ratio is 0.

Final Macro Processing ...

=========================================================================
Final Register Report

Found no macro
=========================================================================

=========================================================================
* Partition Report *
=========================================================================

Partition Implementation Status
-------------------------------

No Partitions were found in this design.

-------------------------------

=========================================================================
* Final Report *
=========================================================================

Clock Information:
------------------
No clock signals found in this design

Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design

Timing Summary:
---------------
Speed Grade: -4

Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 3.692ns

=========================================================================

Process "Synthesize" completed successfully
NotUpToDate:generated file list is cmd
ngdbuild -ise "C:/Xilinx91i/bmsu/bmsu.ise" -intstyle ise -dd _ngo -nt timestamp -i -p xc3s250e-pq208-4 "bmsu.ngc" bmsu.ngd is cmd

Command Line: C:\Xilinx91i\bin\nt\ngdbuild.exe -ise C:/Xilinx91i/bmsu/bmsu.ise
-intstyle ise -dd _ngo -nt timestamp -i -p xc3s250e-pq208-4 bmsu.ngc bmsu.ngd

Reading NGO file "C:/Xilinx91i/bmsu/bmsu.ngc" ...

Checking timing specifications ...
Checking Partitions ...
Checking expanded design ...
ERROR:NgdBuild:604 - logical block 'crm_b' with type 'crm' could not be
resolved. A pin name misspelling can cause this, a missing edif or ngc file,
or the misspelling of a type name. Symbol 'crm' is not supported in target
'spartan3e'.
ERROR:NgdBuild:604 - logical block 'champ_reg_b' with type 'champ_reg' could not
be resolved. A pin name misspelling can cause this, a missing edif or ngc
file, or the misspelling of a type name. Symbol 'champ_reg' is not supported
in target 'spartan3e'.
ERROR:NgdBuild:604 - logical block 'comparator_b' with type 'comparator' could
not be resolved. A pin name misspelling can cause this, a missing edif or ngc
file, or the misspelling of a type name. Symbol 'comparator' is not supported
in target 'spartan3e'.
ERROR:NgdBuild:604 - logical block 'and_gate_b' with type 'and_gate' could not
be resolved. A pin name misspelling can cause this, a missing edif or ngc
file, or the misspelling of a type name. Symbol 'and_gate' is not supported
in target 'spartan3e'.

Partition Implementation Status
-------------------------------

No Partitions were found in this design.

-------------------------------

NGDBUILD Design Results Summary:
Number of errors: 4
Number of warnings: 0


One or more errors were found during NGDBUILD. No NGD file will be written.

Writing NGDBUILD log file "bmsu.bld"...

Process "Translate" failed

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3 Replies
Xilinx Employee
Xilinx Employee
7,067 Views
Registered: ‎06-14-2012

Re: Error while doing implement design

crm , 'champ_reg_b'  or comparator  netlists are not being picked. NGDBuild must be able to locate this file. When using the command line, use the -sd option to point to the directory containing the file

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Newbie pongowri07
Newbie
7,050 Views
Registered: ‎03-18-2014

Re: Error while doing implement design

Where i should use this -sd. please reply me.

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Xilinx Employee
Xilinx Employee
7,044 Views
Registered: ‎06-14-2012

Re: Error while doing implement design

You have to use in Translate properties.

Capture.PNG
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