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1,042 Views
Registered: ‎04-11-2017

Errors during place design

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Getting the following error during the place design 

ERROR: [DRC 23-20] Rule violation (REQP-123) connects_CLKINSEL_VCC_connects_CLKIN1_ACTIVE - ............/..................../........../........../........./ila_mmcm/inst/mmcme3_adv_inst: The MMCME4_ADV with CLKINSEL tied high requires the CLKIN1 pin to be active.

 

I have connected the CLKIN1 to a valid source from a zynq pll

 

I Wanted to provide a 2x clock to the ILA so with the given clock provided the input to a mmcm and conneccted mmcm output to ILA

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Mentor
Mentor
1,245 Views
Registered: ‎02-24-2014

It sounds like there is a connection problem of some sort.   Load the routed design into Vivado,  find your MMCM in the netlist, and hit F4 to generate a schematic of the MMCM..   Then trace the connection on CLKIN1 backwards (by double clicking on the CLKIN1 pin) to see where the driver is located.  

Don't forget to close a thread when possible by accepting a post as a solution.

View solution in original post

1 Reply
Mentor
Mentor
1,246 Views
Registered: ‎02-24-2014

It sounds like there is a connection problem of some sort.   Load the routed design into Vivado,  find your MMCM in the netlist, and hit F4 to generate a schematic of the MMCM..   Then trace the connection on CLKIN1 backwards (by double clicking on the CLKIN1 pin) to see where the driver is located.  

Don't forget to close a thread when possible by accepting a post as a solution.

View solution in original post