12-07-2016 12:05 PM
I am getting the error:
Running physical synthesis...
FATAL_ERROR:1::78:1.3 - Physical Synthesis Failed. For technical support on
this issue, please visit http://www.xilinx.com/support.
Process "Map" failed
with no further information during the implemetation of a design. I tried all of the suggestions found here: https://www.xilinx.com/support/answers/42981.html but nothing helped.
What could be causing this error?
12-07-2016 09:06 PM
Check the following Answer Record:
Make sure you are using supported OS version with the ISE.
12-08-2016 01:42 AM
Try disabling -logic_opt and -register_duplication in MAP settings and see if it helps to overcome the error.
12-08-2016 08:07 AM
I am unable to remove the -logic_opt Combinational Logic Optimization option. I have tried changing the Design Goal to Balanced and Strategy to Xilinx Default (unlocked) but this does not unlock that option. Checking the "unlock" box for other Design Goals/Strategies also fails to unlock this option.
Disabling register duplication does not overcome this error.
12-08-2016 08:09 AM
12-11-2016 10:17 PM
Can you upload the captures showing MAP process properties and "design goals and strategies"?
12-15-2016 12:00 PM
12-15-2016 12:49 PM
12-15-2016 09:49 PM
The option to remove optimization is greyed out even though I am using the "unlocked" strategy. Choosing another strategy and along with the "unlock" option also fails to enable the deselection of optimization. How do I go about deselecting optimization when it appears that I do not have that option? Is there somewhere else other than what I've shown in the screenshots where I can remove optimization?