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Orzica
Observer
Observer
441 Views
Registered: ‎01-02-2021

Hello,

Is better for performance to infer or to instantiate a FIFO? Which way is better?

Thanks!

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syedz
Moderator
Moderator
435 Views
Registered: ‎01-16-2013

@Orzica 

 

I don't think FIFO can be inferred in Vivado. Please check this below post:

https://forums.xilinx.com/t5/Xilinx-IP-Catalog/Can-you-infer-a-FIFO/td-p/960995 

 

--Syed

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syedz
Moderator
Moderator
436 Views
Registered: ‎01-16-2013

@Orzica 

 

I don't think FIFO can be inferred in Vivado. Please check this below post:

https://forums.xilinx.com/t5/Xilinx-IP-Catalog/Can-you-infer-a-FIFO/td-p/960995 

 

--Syed

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
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joancab
Advisor
Advisor
428 Views
Registered: ‎05-11-2015

I most of the times explicitly instantiate to not confuse future users or myself in the future. In terms of speed (if that's what you mean by performance), as long as it works I'm happy. It could happen that an inferred Fifo uses less resources, not sure, being quite a basic building block. It may depend on each particular case and on what one understands by 'performance'

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joancab
Advisor
Advisor
385 Views
Registered: ‎05-11-2015

                                                     

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richardhead
Scholar
Scholar
368 Views
Registered: ‎08-01-2012

@joancab That is a shift register, not a FIFO.

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