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Observer jff118
Observer
5,825 Views
Registered: ‎08-01-2013

FPGA Editor Manual Routing a LUT

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Hello everyone-

 

I am in the middle of debugging a timing problem I'm having in the FPGA.  I know its has to do with clock domains and that if they code was done correctly I wouldn't need to do this, but its not my code and I am just trying to fix it.  Moving forward.

 

I have had this problem in the past where I either want to add some signals to a LUT either to be used with Chipscope or part of another equation.  I don't want to rebuild the entire design because it changes the timing and takes to long.  I have been able to succesfully route signals to PINs via FPGA editor.


HOWEVER, when I try and route a signal to a LUT i end up with this problem show.  The net routes fine in the the fabirc, however the LUT port to the LUT itself becomes disconnected and I can't seem to figure out how to connect the net from pin B3 to the actual LUT pin A3.  I have been searching forever on this and can't seem to find an answer.  Is this even still possible???

 

 

The Design is a Spartan 6 and I'm using ISE13.4 and 14.3 depending on the day :-(

Thanks

JoeLUT Route

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1 Solution

Accepted Solutions
Observer jff118
Observer
7,654 Views
Registered: ‎08-01-2013

Re: FPGA Editor Manual Routing a LUT

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Ok so I have a solution now after playing around a little more.

 

Even though hte equation is already written inside the LUT, when I deleted the net going into the slice the tool deleted the net going into the LUT.

 

I have to open the equation editor and make a change, it didn't even matter where it was but I had to trick the tool to thing something changed.  I just ended up removing the component to the equation I was using and saving.  Then I added it back in and saved again and it worked.  

 

 

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5 Replies
Moderator
Moderator
5,820 Views
Registered: ‎04-17-2011

Re: FPGA Editor Manual Routing a LUT

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Moving to Implementation Board
Regards,
Debraj
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Observer jff118
Observer
5,791 Views
Registered: ‎08-01-2013

Re: FPGA Editor Manual Routing a LUT

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Anybody?????

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Xilinx Employee
Xilinx Employee
5,786 Views
Registered: ‎07-01-2008

Re: FPGA Editor Manual Routing a LUT

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I think the problem is that you have not defined a LUT equation that uses that input. Once you do that I would expect the connectivity to be displayed. Select the F= button to display the LUT equations and edit them.

Observer jff118
Observer
5,778 Views
Registered: ‎08-01-2013

Re: FPGA Editor Manual Routing a LUT

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No thats not the case, the equation is already definted.  In this case there was already a pin defined for that input to the LUT.  I deleted it and added a new net to the PORT on the slice.  However the connection inside the slice is not there anymore.  I didn't have to change the equation inside the LUT since it was already definted.

 

 

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Observer jff118
Observer
7,655 Views
Registered: ‎08-01-2013

Re: FPGA Editor Manual Routing a LUT

Jump to solution

Ok so I have a solution now after playing around a little more.

 

Even though hte equation is already written inside the LUT, when I deleted the net going into the slice the tool deleted the net going into the LUT.

 

I have to open the equation editor and make a change, it didn't even matter where it was but I had to trick the tool to thing something changed.  I just ended up removing the component to the equation I was using and saving.  Then I added it back in and saved again and it worked.  

 

 

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