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Participant
Participant
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Registered: ‎09-27-2019

Found timing loop after synthesis

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tu5.JPG

 

In my RTL code, there is a logic block like the picture describes, the IO_PIN can be selected as the master clock to the logic block, and the logic can also generate the gate clock output to the IO_pin. but when the signal from the IO_PIN is selected as the master clock. the OE=1'b0. the IO pin cannot work as output pin.

but after the synthesis, there is a found timing loop warning message, and the implementation can be successful, there is wrong timing.

when I delete the clock mux, assign the masterclock = other clock  (like the red line arrow )not the IO_PIN . it can synthesis and implement successfully.

how can I do the timing constraint so that I can keep the clock mux?

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132 Views
Registered: ‎01-22-2015

@zhanghefu 

Thanks for taking the time to draw a picture that helps clarify your question.

It is an unusual but interesting question.

First, much of the question is about routing clocks.  So, you should be using clocking components and not using combinational logic (ie. AND-gate, LUTs) for clock routing. 

Try using the following circuit (which is for a 7-Series FPGA) instead of what you have shown.  This circuit consists of a BUFGMUX called BFMX1, an ODDR, and an IOBUF - all of which are described in UG953.  You should not have a timing loop problem with this circuit.

CLKIO_concept.jpg

Note that your second clock is routed to pin, I1, of the BUFGMUX.  Also, your Gate_clock control signal is routed to the T-pin of the IOBUF.

I see that you and driesd have talked elsewhere about timing constraints for the BUFGMUX.  Please also refer to pages 43-44 of UG903(v2020.1) for a discussion of BUFGMUX timing constraints.  You should also place a create_clock constraint on the bidirectional port called CLKIO where a clock enters the FPGA.

Cheers,
Mark

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Scholar
Scholar
221 Views
Registered: ‎08-07-2014

@zhanghefu,

Is the IO pin planning and board layout done? Is it a must that the gated_clock signal remains within the FPGA fabric?

If not, I have this idea to eliminate the use of two buffers with OE and IE.

1. One clock MUX input: gated_clock_out --> o/p FPGA pin --> board level loop-back (FPGA o/p pin to FPGA i/p pin, make sure to use clock-capable IOs) --> i/p FPGA pin --> clock MUX i/p

2. Another clock MUX input: IO_Pin --> clock MUX i/p

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Participant
Participant
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Registered: ‎09-27-2019

 

Hi,

      Thank you for your answer!

      I know your idea, you mean I'd better separate the pins, one is used to the clock_pin -clock_mux, another is used to gate_clock output.

      the previous picture is not very clear.

      I means the FPGA IO pin can be used clock_input, and clock out. when the FPGA is used to the clock input, the gate_clock will not work.

      this logic function can be modified, do you have good idea to do the timing constraint? 

 

tu5.JPG

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Highlighted
133 Views
Registered: ‎01-22-2015

@zhanghefu 

Thanks for taking the time to draw a picture that helps clarify your question.

It is an unusual but interesting question.

First, much of the question is about routing clocks.  So, you should be using clocking components and not using combinational logic (ie. AND-gate, LUTs) for clock routing. 

Try using the following circuit (which is for a 7-Series FPGA) instead of what you have shown.  This circuit consists of a BUFGMUX called BFMX1, an ODDR, and an IOBUF - all of which are described in UG953.  You should not have a timing loop problem with this circuit.

CLKIO_concept.jpg

Note that your second clock is routed to pin, I1, of the BUFGMUX.  Also, your Gate_clock control signal is routed to the T-pin of the IOBUF.

I see that you and driesd have talked elsewhere about timing constraints for the BUFGMUX.  Please also refer to pages 43-44 of UG903(v2020.1) for a discussion of BUFGMUX timing constraints.  You should also place a create_clock constraint on the bidirectional port called CLKIO where a clock enters the FPGA.

Cheers,
Mark

View solution in original post

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Participant
Participant
78 Views
Registered: ‎09-27-2019

Thank you very much, it's a good idea! I will try it!

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