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Participant
Participant
2,515 Views
Registered: ‎03-12-2018

Generate bitstream

I'm using Vivado 2017.3.1. I routed a design that failed timing. I still want to generate a bitstream in spite of the timing failures. (By the way, the timing failures are very, very small and I'm certain the design when I download it to my FPGA eval board.) When I generate the bitstream, it fails. How do I instruct Vivado to ignore the timing failures and generate the bitstream?

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Explorer
Explorer
2,498 Views
Registered: ‎03-31-2016

Re: Generate bitstream

What errors are you seeing during bitstream generation?

 

Vivado doesn't generally error just because the design failed to meet timing.

 

The only license issue or DRC should cause it to fail to generate a bitstream.

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2,476 Views
Registered: ‎01-22-2015

Re: Generate bitstream

I am also using Vivado Webpack v2017.3.1.   In project mode, I find that it generates the bitstream when timing analysis fails.

 

If you are using Tcl commands to generate the bitstream then try the following:

    write_bitstream -force <filename> 

 

Without the -force option, Vivado will not overwrite an existing bit-file and will instead throw an error.

 

Mark

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Participant
Participant
2,346 Views
Registered: ‎03-12-2018

Re: Generate bitstream

@necare81

 

The errors are timing failures.

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Participant
Participant
2,343 Views
Registered: ‎03-12-2018

Re: Generate bitstream

markg@prosensing.com

 

I'm using the GUI. I guess I'll try looking through Settings (under the Bitstream option) to see where I could issue the -force option.

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Explorer
Explorer
2,340 Views
Registered: ‎03-31-2016

Re: Generate bitstream

@bjackson_ost what is the specific error seen during bitstream generation?  Without specific messages no one is going to be able to help.  You probably need to look at all the warning/errors in the messages tab of the GUI to start with, it should have very specific reasons for not generating a bitstream but sometimes the GUI message extraction doesn't work properly and you need to go check the actual text logs.

 

Not meeting timing does not prevent bitstream generation.  If you do run "implementation to step generate bitstream" it might stop for a timing failure after implementation but you can just run the generate bitstream step again without running through all of implementation(assuming you haven't change other stuff that would put the design out of date).

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Participant
Participant
2,331 Views
Registered: ‎03-12-2018

Re: Generate bitstream

@necare81

 

I've since resolved my timing issues and am able to successfully generate a bitstream. Suffice to say, the timing issues were coming the DDR controller I generated using the Xilinx MIG tool.

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Registered: ‎11-05-2019

Re: Generate bitstream

Hey @necare81, how did you solve the issue? What settings did you modify regarding the MIG? Could you please provide me with some details, I am also facing a similar issue.

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