08-04-2018 09:14 AM
I'm using Vivado 2017.3.1. I routed a design that failed timing. I still want to generate a bitstream in spite of the timing failures. (By the way, the timing failures are very, very small and I'm certain the design when I download it to my FPGA eval board.) When I generate the bitstream, it fails. How do I instruct Vivado to ignore the timing failures and generate the bitstream?
08-04-2018 10:54 AM
What errors are you seeing during bitstream generation?
Vivado doesn't generally error just because the design failed to meet timing.
The only license issue or DRC should cause it to fail to generate a bitstream.
08-04-2018 04:58 PM
I am also using Vivado Webpack v2017.3.1. In project mode, I find that it generates the bitstream when timing analysis fails.
If you are using Tcl commands to generate the bitstream then try the following:
write_bitstream -force <filename>
Without the -force option, Vivado will not overwrite an existing bit-file and will instead throw an error.
08-13-2018 08:29 AM
08-13-2018 08:41 AM
@bjackson_ost what is the specific error seen during bitstream generation? Without specific messages no one is going to be able to help. You probably need to look at all the warning/errors in the messages tab of the GUI to start with, it should have very specific reasons for not generating a bitstream but sometimes the GUI message extraction doesn't work properly and you need to go check the actual text logs.
Not meeting timing does not prevent bitstream generation. If you do run "implementation to step generate bitstream" it might stop for a timing failure after implementation but you can just run the generate bitstream step again without running through all of implementation(assuming you haven't change other stuff that would put the design out of date).
08-13-2018 08:51 AM
I've since resolved my timing issues and am able to successfully generate a bitstream. Suffice to say, the timing issues were coming the DDR controller I generated using the Xilinx MIG tool.