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Visitor xsilverx
Visitor
5,531 Views
Registered: ‎11-19-2012

Generating bitstream with Probes.

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Hello!

 

Vivado 2014.4 : WebPACK Edition

 

I add probe using xilinx::debugutils::add_probe command form TCL store Debug tools in fully routed design. It works and I see respective OBUF connected to probe pin in Implemented design view. But when I run Generate Bitstream command, I have a message with question about saving changes (probe) in my original design.

1) If I choose Don't save, generated bitstream file doesn't contain my probe, only original design.

2) If I choose Save, Vivado add "probe" constraints in active XDC file and rerun all design steps. But there is no probe in bitstream file too.

I want to route probe in my fully routed design in addition without rerun overall routing and generate bitstream with it.

Incremental compile also rerun all design steps.
How can I generate bitstream without rerun design steps and without saving probe modifications in my original design (similar to FPGA editor in ISE)?

I want to minimize routine and time to adding probe.

P.S. Sorry for my "English".

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1 Solution

Accepted Solutions
Xilinx Employee
Xilinx Employee
10,535 Views
Registered: ‎09-20-2012

Re: Generating bitstream with Probes.

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Hi @xsilverx

 

After running add_probe command from TCL console on Implemented design, run write_bitstream test.bit command in the same console. This will generate bit file for modified design.

Thanks,
Deepika.
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Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)
2 Replies
Explorer
Explorer
5,512 Views
Registered: ‎04-23-2014

Re: Generating bitstream with Probes.

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I do not use tcl, so the following may not apply to it, but still:

When I select a net for debug, I run synthesis first, then open it and perform Set UP Debug. After that I generate bitstream including performing implementation.

 

This is the message that pops up after validating design before synthesis:

WARNING: [BD 41-1634] Updates have been made to one or more nets marked for debug. It is required to open the synthesized design and use the Set Up Debug wizard to insert, modify or delete Debug Cores. Failure to do so could result in critical warnings and errors in the implementation flow. 
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Xilinx Employee
Xilinx Employee
10,536 Views
Registered: ‎09-20-2012

Re: Generating bitstream with Probes.

Jump to solution

Hi @xsilverx

 

After running add_probe command from TCL console on Implemented design, run write_bitstream test.bit command in the same console. This will generate bit file for modified design.

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)