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prodanny1
Visitor
Visitor
751 Views
Registered: ‎04-18-2020

HD.ISOLATED_EXEMPT

Hi,

I have read the XAPP1222 and the XAPP1256.

As I understood the constrain HD.ISOLATED_EXEMPT is this way:

if I have an Isolated pblock... and I want some signal to be routed into (or from) the Isolated pblock, I do the HD.ISOLATED_EXEMPT constrain to this specific signal.

Am I write? or there is other meaning?

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8 Replies
rshekhaw
Xilinx Employee
Xilinx Employee
736 Views
Registered: ‎05-22-2018

Hi @prodanny1 ,

Correct!

Nets driven by cells marked HD.ISOLATED_EXEMPT are exempt from inter-region isolation rules. An intra-region route cannot enter a fence tile or an isolated tile of another isolation group unless it is driven by a cell marked with the HD.ISOLATED_EXEMPT property.

Thanks,

Raj

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hongh
Moderator
Moderator
713 Views
Registered: ‎11-04-2010

Hi, @prodanny1 ,

Generally only global clock signal will be considered to add HD.ISOLATED_EXEMPT property.

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prodanny1
Visitor
Visitor
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Registered: ‎04-18-2020

thanks for your answer that ensure my understanding...

Now I have some problem:

In my design, there are 5 modules. Only 2 of them are ISOLATED.

When I run tne Implementation, I have houndres of critical warnings ,All from the same type named "Constraints 18-5257".

All this warnings goes for signals/routs/primitives that have NO ANY connection at all to the Isolated module.

For an example, This warnings goes:

IDF: Net design_1_i/rx_tx_LVDS/rx_LVDS/inst/data_in_to_device[6] is being treated as a Global or Global Clock net. It cannot be guaranteed to be Contained within an Isolated Module. This can be due to a LOC or PACKAGE_PIN constraint on the driver cell: design_1_i/rx_tx_LVDS/rx_LVDS/inst/pins[2].iserdese2_master. It may be necessary to apply the HD.ISOLATED_EXEMPT property to this cell or adjust your Pblock floorplan or cell constraints to ensure containment of this net.

On this exampe it talks about the "rx_tx_LVDS" module which is Not Isolated, and have no connection to isolated modules.

 

The Question is why? and how do I fix it?

(I am not sure that the HD.Isolated_exempt is the write option here because of the text that marked in RED above)

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rshekhaw
Xilinx Employee
Xilinx Employee
627 Views
Registered: ‎05-22-2018

Hi @prodanny1 ,

In IDF flow the pblock will have EXCLUDE_PLACEMENT and CONTAIN_ROUTING set to 1 in order to keep the routing and placement inside the PBLOCK. Can you please check whether they are set, you can check them under PBLOCK properties.

Thanks,

Raj

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prodanny1
Visitor
Visitor
610 Views
Registered: ‎04-18-2020

thanks for the tip...

I set them to '1' ,then I put all my HD.Isolate_Exempt into a COMMENT in the constrain file (XDC) but unfortunatly I still got houndreds of critical warnings from the same type.

what do I miss?

 

what this two "EXCLUDE_PLACEMENT and CONTAIN_ROUTING" means in the pblock?

 

 

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rshekhaw
Xilinx Employee
Xilinx Employee
601 Views
Registered: ‎05-22-2018

Hi @prodanny1 ,

CONTAIN_ROUTING restricts the routing of signals contained within a Pblock to use routing resources within the area defined by the Pblock. This prevents signals inside the Pblock from being routed outside the Pblock, and increases the reusability of the
design.

EXCLUDE_PLACEMENT is used to indicate that the device resources inside ofthe area defined by a Pblock should only be used for logic contained in the Pblock.

Thanks,

Raj

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prodanny1
Visitor
Visitor
588 Views
Registered: ‎04-18-2020

I see...

So this 2 properties are not helping me because my problem is not with the logics and routes that inside the isolated pblocks.

My problem is with all my other design that is outside from the isolated pblock that have no connection to the Isolated pblock and I still have a critical warnings for them as I mentioned.

where is the mistake that I made?

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hongh
Moderator
Moderator
468 Views
Registered: ‎11-04-2010

Hi, @prodanny1 ,

You can try to create a new isolated range and put the rest of the logic into it.

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