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Explorer
Explorer
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Registered: ‎04-28-2013

Help , I want to know some detail information about xc7v2000t!

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I know  that the 2.5D xc7v2000t has 4 dies in it . But I want to know the detail information about Clock Regions on each die.

 

eg . Total Clock regions from  X0Y0 to X1Y11.

Is that true that :  Clock region X0Y0 to X0Y5    belong to die_0,

                               Clock region X0Y6 to X0Y11 belong to die_1,

                               Clock region X1Y0 to X1Y5    belong to die_2,

                               Clock region X1Y6 to X1Y11 belong to die_3,

 

I need this information because I want to optimize my design's timing. I want to put some critical timing logic on one die other than across dies.

 

 

 

 

nonsense
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Xilinx Employee
Xilinx Employee
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Registered: ‎06-20-2008

I have attach a doc which I use to keep track of which Region/SLR the BUFGs, MMCMs and PLLs are located in. 

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Xilinx Employee
Xilinx Employee
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Registered: ‎01-03-2008

No this is not correct.  Each die will have both X0 and X1 (this is the region to the left of the center clock spine and region to the right of the center clock spine) and then one region per IO bank (3 vertical IO banks in each SLR)

 

SLR 3 - X0Y9 to X1Y11

SLR 2 - X0Y6 to X1Y8

SLR 1 - X0Y3 to X1Y5

SLR 0 - X0Y0 to X1Y2

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Xilinx Employee
Xilinx Employee
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Registered: ‎06-20-2008

I have attach a doc which I use to keep track of which Region/SLR the BUFGs, MMCMs and PLLs are located in. 

View solution in original post

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Explorer
Explorer
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Registered: ‎04-28-2013

Thanks mcgett and llewis.  Both of you help me much .

nonsense
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Anonymous
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Hi,

 

I'm using KC705 with XC7K325T-2FFG900C FPGA.

I met a problem that i need to know the clock region and which region the BUFGS are located in.

I have tried the 7 series_clocking,pins and packages and other spec, but i didn't find any about this. 

Can you show me where i can find these information?

Another thing is i'm using XPS to do customized ip core, but i can't find fpga editor, can you also show me that?

Thanks in advance.

 

Jason

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎01-03-2008

> I met a problem that i need to know the clock region and which region the BUFGS are located in.

 

BUFGs are not located in a clock region.  They are global.

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Anonymous
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But i met a problem is

Unroutable Placement! A MMCM / BUFGCTRL clock component pair have been found that are not placed at a
routable MMCM / BUFGCTRL site pair. The MMCM component
<clock_generator_0/clock_generator_0/MMCMextra_INST/MMCM_ADV_inst> is placed at site <MMCME2_ADV_X1Y1>. The
corresponding BUFGCTRL component <clock_generator_0/clock_generator_0/MMCM0_CLKOUT0_BUFG_INST> is placed at site <BUFGCTRL_X0Y27>.

 I don't find information about BUFGCTRL_X0Y27 and MMCME2_ADV_X1Y1.

Where i can find that?

Thanks.

 

Jason

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Xilinx Employee
Xilinx Employee
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Registered: ‎01-03-2008

Do you add placement location constraints to both the MMCM and BUFGCTRL?  If not is there another MMCM in the design that is driving the other input of the BUFGCTRL?

There is restriction that the MMCM/PLLs can only drive the BUFG in their top/bottom half of the device.  This restriction is noted in Table 1-1 of the 7 Series Clock User Guide UG472.  There are 32 BUFGs in the device and locations X0Y0:X0Y15 are in the bottom half and X0Y16:X0Y31 are in the top half.    Figure 1-5 in the 7 Series FPGAs Packaging and Pinout User Guide UG475 shows the delination of top/bottom for the 7K325T and the MMCM locations.

 

BUFGCTRL_X0Y27 is in the top half and the MMCM_X1Y1 is in the bottom half next to bank 33.  This is why you are getting this placement error message.

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Anonymous
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Thanks for your reply.

I don't use any constrants to MMCM or BUFGCTRL. I'm only use one MMCM. I don't know why this happens.

Any idea on how to debug and solve this?

Thanks.

 

Jason.

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Xilinx Employee
Xilinx Employee
8,984 Views
Registered: ‎11-28-2007

@Anonymous wrote:

Hi,

 

I'm using KC705 with XC7K325T-2FFG900C FPGA.

I met a problem that i need to know the clock region and which region the BUFGS are located in.

I have tried the 7 series_clocking,pins and packages and other spec, but i didn't find any about this. 

Can you show me where i can find these information?

Another thing is i'm using XPS to do customized ip core, but i can't find fpga editor, can you also show me that?

Thanks in advance.

 

Jason

 


Hi Jason,

 

please don't post any messages on threads that are unrelated to your question!

Your question is not related to the xc7v2000t, but the KC705 and Kintex-7 325t....

 

To debug your problem:

1) verify if indeed you don't have any placement constraints on the BUFG or MMCM: open the synthesized design and do "write_xdc" to dump the constraints in memory. Then verify if there aren't any LOC constraints that you didn't expect.

2) verify any constraints on sources and loads: in the synthesized design, create schematic of the BUFG and MMCM and explore what the source is and loads are and verify if there aren't any placement LOC constraints on them, driving the placement of the BUFG and/or MMCM

 

 

Best regards

Dries

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Anonymous
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Hi,

 

Thanks for your reply.

I'm using XPS to do the whole project, can you tell me how to use the "write_xdc"? and this command seems convert 

ucf file to xdc file? why do i do that?

After that, i still veriy the constraints in the ucf file?

 

Thanks.

Jason

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Xilinx Employee
Xilinx Employee
3,119 Views
Registered: ‎11-28-2007

Hi Jason,

 

XDC is in Vivado.

In your case, you can open PlanAhead from ISE or open the separate FPGA-editor tool

 

If you have any follow-up questions, please open a new thread as none of these are related to the original xc7v2000t topic.

 

 

Thanks

Dries

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