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khaalidi
Participant
Participant
411 Views
Registered: ‎01-20-2021

How can I constraint placement of design inside a specific slice using the LOC constraint without mentioning BEL and LOC for each Cell.

My design takes up 4 LUT so it can be placed in one Slice. I want the placement in specific locations. Since my design is parametric, I want to just instantiate multiple instances of the Module and pass the Slice Location in a parameter as LOC=SLICE_XnYm .  I don't wanna mention which Cell is taking which LUT.

I want to only provide Slice information.

 

with only using the LOC=SLICE_XnYm  inside the module, It show some some LUTS in Cyan and some in orange. Cyan as Placed and Orange as Fixed. Will it make any issue?

`timescale 1ns / 1ps

(* keep_hierarchy = "yes" *) module RO
#(parameter SLICE = "SLICE_X43Y0")
(
(* dont_touch = "true" *) input enable,
(* dont_touch = "true" *) output clk

);
(* LOC = SLICE *)
// Intermediate Connections
(* dont_touch = "true" *) wire w1,w2,w3;

(* dont_touch = "true" *) and #2 (w1, enable, clk);
(* dont_touch = "true" *) not #1 (w2,w1);
(* dont_touch = "true" *) not #1 (w3, w2);
(* dont_touch = "true" *) not #1 (clk, w3);

endmodule

 

`timescale 1ns / 1ps


module top(
        output out
    );

wire enable, clk1, clk2;

 RO  #(.SLICE("SLICE_X0Y99")) R0(enable, clk1);    
 RO  #(.SLICE("SLICE_X0Y98")) R1(enable, clk2);
endmodule

asdsadsa.PNG

 

❝Analogue by birth, Digital by design.❞
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khaalidi
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Registered: ‎01-20-2021

Update: If I use SLICEL slices then the placement is OK, but It's status is still  Fixed not Placed.

❝Analogue by birth, Digital by design.❞
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Registered: ‎01-22-2015

@khaalidi 

Please see the RLOC property that is described in UG903(v2020.1), starting on page 163.

Cheers, Mark

khaalidi
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Registered: ‎01-20-2021

Thanks,

Why is the placement Ok for SLICEL slices but not for SLICEM?

SLICELSLICEL

 

SLICEMSLICEM

❝Analogue by birth, Digital by design.❞
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