08-27-2013 10:08 AM
In this picture, i want to know to use CLK_B instead CLK.
myFlop : process (CLK) is
if falling_edge(CLK) then
q <= d;
end process myFlop;
08-29-2013 10:52 AM
You can use the primitives in the FPGA to invert a clock that is much stable .
Why would you want to do that when the code snippet I provided does exactly that, without the unnecessary instantiation of primitives?
09-04-2013 10:38 AM
Use FPGA editor change it, I guess you want do a ECO on a exist nice file.
That's very dangerous. Then the source doesn't match what gets loaded into the FPGA, and the next guy who has to deal with this will wonder what the hell is going on.