08-02-2017 09:11 PM
I am new to clocking in Virtex. My device is a Virtex6 on the ML605 devkit.
From the Planahead as well as the pin datasheet, the L16 is an MRCC pin.
So in the UCF, I did this:
NET "refclk" LOC = L16;
The verilog is just a simple connection to the MMCM:
However, I got this error:
ERROR:Place:1155 - A clock IOB / MMCM clock component pair have been found that
are not placed at an optimal clock IOB / MMCM site pair. The clock IOB
component <refclk> is placed at site <L16>. The corresponding MMCM component
<pll/mmcm_adv_inst> is placed at site <MMCM_ADV_X0Y0>. The clock IO can use
the fast path between the IOB and the Clock Manager if a) the IOB is placed
on a Local Clock Capable IOB site in the same horizontal clock region pair as
the MMCM site (fastest dedicated path), or b) the IOB is placed on a ....
Any advice on how to fix this?
I also went ahead to fix the location of the MMCM:
INST "pll/mmcm_adv_inst" LOC = "MMCM_ADV_X0Y8";
But similar error persists.
I thought the MRCC can be used as a driver for the MMCM.
Please help, thanks!
08-02-2017 09:24 PM
The pin in question is an MRCC in bank 36. Bank 36 is an outer bank of the Virtex-6. The CMT (MMCM/PLL) can only be fed by GC pins or by MRCC pins in the inner banks; there is no connection to the global clocking from the outer banks.
08-02-2017 10:49 PM
Thanks for the reply.
1) what is the MRCC in the outer bank used for? Can I connect it to a BUFR, and then use the BUFR to drive the clkin of an MMCM/PLL?
2) how do I know which bank is inner or outer? Using my example, which bank's MRCC/SRCC should I use to connect to the PLL in X0Y9 or X0Y8?
08-02-2017 11:08 PM
I looked at the FPGA packaging and pinout document for Virtex6, fig 1-3, page 22, and bank 36 is on the IOCR banks, and there is dotted line from bank 36 to the MMCM09 and MMCM08.
It looks like bank36 should be able to drive the MMCMs, no?
08-03-2017 05:16 AM
Sorry - you are right, L16 is in an IOCR, and the IOCR (I/O Center Right) do have connections to the MMCMs.
HOWEVER, L16 is the N side of the differential pair, not the P side. The N side of an MRCC can only be used as the N side of a differential clock - it cannot be used as a single ended clock on its own - only the P side of a CC or GC pair can be used for a single ended clock. So K16 would be OK, but not L16.
The outer column CC pins are for "ChipSync" clocking. ChipSync clocking is used primarily for source synchronous interfaces. The clock goes directly to the BUFIO and BUFR, which drive the IOB (IDDR and ISERDES) in the same clock region and the logic in the same clock region respectively. The BUFR can clock both the BUFG (in the same half) and the MMCM (in the same clock region, one above or one below), but these connections are not skew compensated - even by the MMCM. As a result, you have to view the resulting clocks (from the BUFR and the BUFG) as mesochronous; you need a clock domain crossing (CDC) circuit to move data between them.
The complete list of "what can connect to what" is shown in UG362, Appendix A, Table A-1.