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Anonymous
Not applicable
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How to determine what part of the design consumes the most resources?

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I am working on a large FPGA design, and I am very close to the resource limits of the FPGA that I am currently using, the Xilinx LX16 in the CSG225 package. (-2)

 

The design is also almost complete, however at the moment it will no longer fit in the FPGA. I can turn off parts to get it to fit, however I need to reduce the resource usage in order to complete the design and have it meet timing and size requirements.

 

I would like to know if there are any tools our reports that can help me identify which parts of my design are consuming the most resources. My design is not partitioned, and is split over about a dozen or more VHDL modules.

 

Xilinx timing reports are fantastic, but now I need to know where I can get my best bang-for-buck in terms of space saving.

I also have a hard time telling which type of resources I'm running out of, or what effects those resources.

 

Another annoyance is that as the design gets larger, components that used to meet timing are starting to fail because their placement is no longer as ideal.

 

Currently, I use the Post-Place and Route Static timing reports, and I use SmartXplorer. I'm using design strategies to optimize for timing.

 

After turning off part of my design to get it to fit, here are some of the results:

slice register utilization: 42%

slice LUT utilization: 96%

number of fully used LUT-FF pairs: 38%

 

Does this mean I'm light on registers, but heavy on logic usage?

 

Are there tools to help developers optimize for area, or at least give them more insight into their code?

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Xilinx Employee
Xilinx Employee
16,558 Views
Registered: ‎09-20-2012

Hi,

 

In ISE MAP properties, you can enable detail reporting. This generates module level utilization report which may help you in finding out the module which is using high resources.

 

Capture.PNG

Thanks,

Deepika.

Thanks,
Deepika.
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Xilinx Employee
Xilinx Employee
16,559 Views
Registered: ‎09-20-2012

Hi,

 

In ISE MAP properties, you can enable detail reporting. This generates module level utilization report which may help you in finding out the module which is using high resources.

 

Capture.PNG

Thanks,

Deepika.

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)

View solution in original post

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Scholar
Scholar
10,936 Views
Registered: ‎06-14-2012

Yes you are right in telling that you are light on registers, but heavy on logic usage.

 

Another things to reduce slice consumption is to move them to BRAMs. Try using -bp switch with map.

You could also explore -c  for the packing factor.

 

Hope this helps.

 

Regards

Sikta

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Professor
Professor
10,919 Views
Registered: ‎08-14-2007

In order to get a better view of per-module usage you might also need to set "Keep Hierarchy" to true or soft.  Note that this could increase the overall device usage, so use it only for determining the areas to focus on.  Also I'd suggest specifying a larger device while you are going through this exercise.  This shortens the run time and allows you to see more complete data when your design would overmap the LX16 device.

-- Gabor
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Anonymous
Not applicable
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Module Level Utilization is exactly what I need. After running this, I opened the Design Summary, and found everything I need in Design Summary -> Module Level Utilization. Thanks Sikta and Gabor too! I'm definitely going to use a larger device to route and test with until the full design fits.
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