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Contributor
Contributor
4,995 Views
Registered: ‎04-17-2017

How to find clock compatible pin

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Hi,

 

    I want to transfer some data from microcontroller(master) to FPGA(slave) using SPI protocol. So in my top module, I have an input port SCK(SPI master clock) to be connected to microcontroller. 

 

   I am using Nexy4 DDR digital circuit development platform, the only connector I can find on board is Pmod ports. So I set one of connector as SCK. When implementation, it failed, saying this pin can't routed to clock_buffer. I managed to work around by inserting set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets sck_IBUF], though vivado still telling me poor placement for routing between an IO pin and BUFG. I think it will prevent me from setting proper timing constraints.

  

  Is there any clock compatible pin hiding in these six Pmod connectors?

 

 n4v.png

 

Error:

 

[DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. 
Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin.
This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design.
sck_IBUF_inst (IBUF.O) is locked to IOB_X1Y120
sck_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y1

 

 

 

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Accepted Solutions
Explorer
Explorer
8,248 Views
Registered: ‎07-14-2014

Re: How to find clock compatible pin

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Hi,

 

You need to look at the schematic for the Nexys4 and find which pins those PMOD connectors attach to on the FPGA.

 

If the pin name has MRCC or SRCC (e.g IO_L11P_T1_SRCC) in it then it is a clock capable pin. SRCC is Single Region Clock Capable and MRCC is MultiRegion Clock Capable. Either pin type should be sufficient for what you need to do in this case.

 

Regards

 

Simon

3 Replies
Explorer
Explorer
8,249 Views
Registered: ‎07-14-2014

Re: How to find clock compatible pin

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Hi,

 

You need to look at the schematic for the Nexys4 and find which pins those PMOD connectors attach to on the FPGA.

 

If the pin name has MRCC or SRCC (e.g IO_L11P_T1_SRCC) in it then it is a clock capable pin. SRCC is Single Region Clock Capable and MRCC is MultiRegion Clock Capable. Either pin type should be sufficient for what you need to do in this case.

 

Regards

 

Simon

Adventurer
Adventurer
4,369 Views
Registered: ‎02-14-2009

Re: How to find clock compatible pin

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Hi!

 

You can find clk capable pin via tcl.

For example:

get_property IS_CLK_CAPABLE [get_package_pins {AA8 Y19 AA9}]

 

Adventurer
Adventurer
4,055 Views
Registered: ‎02-14-2009

Re: How to find clock compatible pin

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Just my two cents: output of tcl command is in alphabetical order, be aware!

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