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Visitor
Visitor
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Registered: ‎10-06-2016

How to get preliminary resource estimation/utilization of a submodule before completing the full design?

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I'm at a very preliminary stage of my design, in which i need to assess whether the algorithm i'd like to implement on FPGA can actually fit into the FPGA I have available. Is there a quick way to get the resource utilization report of my custom VHDL code, without inferring the complete design (which would need to include IO ports, interfaces, etc...and is not yet implemented)? I just want to get an estimation of my submodule containing the core algorithm, which at the end will use most of the resources of the FPGA.

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Voyager
Voyager
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Registered: ‎06-20-2012

@alefer85 

synth_design -mode out_of_context

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Voyager
Voyager
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Registered: ‎06-20-2012

Well set the submodule as top and compile.

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Visitor
Visitor
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Registered: ‎10-06-2016

@calibra Most of the time in this way you get an error, since Vivado tries to map the ports of my submodule to the FPGA IO pins, which are normally not enough. Is there a way to avoid this, so that Vivado doesn't consider the submodule as a top level module? i just want to know the resource utilization (DSP slices, LUTs, BRAMs) without considering the IO pins.

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Moderator
Moderator
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Registered: ‎03-16-2017

@alefer85 

For that., you can run report_utilization -hierarchical tcl command in tcl console after synthesis gets completed. (which will be independent of IO pins and its constraints.)

 

Regards,
hemangd

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Voyager
Voyager
357 Views
Registered: ‎06-20-2012

@alefer85 

synth_design -mode out_of_context

== If this was helpful, please feel free to give Kudos, and close if it answers your question ==

View solution in original post

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Visitor
Visitor
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Registered: ‎10-06-2016

@calibra Bingo! that worked. Thank you.

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