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Visitor zzmzc333
Visitor
1,866 Views
Registered: ‎01-27-2018

How to instantiate a hard macro in Verilog

Hi!

 

I  am trying to instantiate a hard macro in Verilog code but it gives some errors:

 

=ERROR:NgdBuild:76 - File "D:\macro\macro/c_OBUF.nmc" cannot be merged into block
ERROR:NgdBuild:604 - logical block 'U0' with type 'c_OBUF' could not be
   resolved. A pin name misspelling can cause this, a missing edif or ngc file,
   case mismatch between the block name and the edif or ngc file name, or the
   misspelling of a type name. Symbol 'c_OBUF' is not supported in target
   'spartan6'.

 

The name of the hard macro is c_OBUF. I appreciate any advice you have.

 

Thanks!

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7 Replies
Scholar jmcclusk
Scholar
1,862 Views
Registered: ‎02-24-2014

Re: How to instantiate a hard macro in Verilog

This is just a guess, but I think you should remake the hard macro using all lower case for the names and pins.  There may be some case sensitivity here.

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Visitor zzmzc333
Visitor
1,836 Views
Registered: ‎01-27-2018

Re: How to instantiate a hard macro in Verilog

I think you are right. I renamed the macro with all lowercase letters. This time it passed the translate. But map gave me some new errors:

ERROR:Place:835 - Given the original pre-placement, no legal placements can be
   found for 1 group(s). The following is the description of these group(s). The
   relative offsets of the components are shown in brackets next to the
   component names.
ERROR:Pack:1654 - The timing-driven placement phase encountered an error.

Do you have any suggestions? Thank you.

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Scholar jmcclusk
Scholar
1,831 Views
Registered: ‎02-24-2014

Re: How to instantiate a hard macro in Verilog

This has something to do with your hard macro design, which is probably involved in IO buffers, given the naming.   Are you placing a large number of macros?  or just one?   and is it in the same place on the die as you used in FPGA editor?

Don't forget to close a thread when possible by accepting a post as a solution.
Visitor zzmzc333
Visitor
1,813 Views
Registered: ‎01-27-2018

Re: How to instantiate a hard macro in Verilog

I just tried one really simple case. There is just one small hard macro which only occupies one slice. I am not sure where is it placed because the design can not pass the implementation (it stopped at "Map" because of those errors).

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Visitor zzmzc333
Visitor
1,796 Views
Registered: ‎01-27-2018

Re: How to instantiate a hard macro in Verilog

Thanks for all the helps, my design passed the synthesis and translate but the it stopped at map with these new errors:

ERROR:Place:835 - Given the original pre-placement, no legal placements can be
   found for 1 group(s). The following is the description of these group(s). The
   relative offsets of the components are shown in brackets next to the
   component names.
ERROR:Pack:1654 - The timing-driven placement phase encountered an error.

I could not solve this though I have tried many things. I have also searched some similar posts from xilinx website but the solution accepted is hard to understand for me. Does anyone have some advice? Thank you very much!

 

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Scholar jmcclusk
Scholar
1,792 Views
Registered: ‎02-24-2014

Re: How to instantiate a hard macro in Verilog

Let's go back to basics here..   What problem are you trying to solve with a hard macro?

Don't forget to close a thread when possible by accepting a post as a solution.
Visitor zzmzc333
Visitor
1,786 Views
Registered: ‎01-27-2018

Re: How to instantiate a hard macro in Verilog

I think what I want to do is figuring out the correct way to use a hard macro in my verilog. I have tried many ways but they are all stopped when running "Implement Design" by the errors mentioned above.

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