09-11-2014 01:13 PM
I have a microblaze design and it works fine for certain verilog code. If I did simeple changes like adding a register for read back, then the simulation totally messed up. I am not quite sure what caused it but it is probably related to the microblaze memory. I believe the clock timing constrains are already in place, there's nothing I can do to fix it!
I am wondering if there's a way to lock the implementation placement so it can be used for the future changes.
09-11-2014 07:40 PM
Please refer to the following AR. The methodology also applies to Vivado.
09-12-2014 03:04 AM
If it's just about locking a design, you might want to look at the TCL command "lock_design" (see ug835).
I'm using this command to lock my "golden" static design in my partial reconfiguration TCL flow.
09-12-2014 12:32 PM
Thanks guys! It turns out the problem is caused by Vivado 2014.1. I ungrade to Vivado 2014.2 and the implementation is consistent now!