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Anonymous
Not applicable
10,923 Views

How to lock placement for Vivado design

I have a microblaze design and it works fine for certain verilog code. If I did simeple changes like adding a register for read back, then the simulation totally messed up. I am not quite sure what caused it but it is probably related to the microblaze memory. I believe the clock timing constrains are already in place, there's nothing I can do to fix it!

 

I am wondering if there's a way to lock the implementation placement so it can be used for the future changes.

 

Tony

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Xilinx Employee
Xilinx Employee
10,909 Views
Registered: ‎07-16-2008

Re: How to lock placement for Vivado design

Please refer to the following AR. The methodology also applies to Vivado.

http://www.xilinx.com/support/answers/40903.html

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Explorer
Explorer
10,895 Views
Registered: ‎07-14-2008

Re: How to lock placement for Vivado design

If it's just about locking a design, you might want to look at the TCL command "lock_design" (see ug835).

 

I'm using this command to lock my "golden" static design in my partial reconfiguration TCL flow.

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Anonymous
Not applicable
10,881 Views

Re: How to lock placement for Vivado design

Thanks guys! It turns out the problem is caused by Vivado 2014.1. I ungrade to Vivado 2014.2 and the implementation is consistent now! 

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