cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
zengqh
Adventurer
Adventurer
532 Views
Registered: ‎01-10-2019

How to reduce clock source latency

I use VCU108 Development board, using high speed interface output clock Userclk2 in x, but I found the clock source delay is very large, how to reduce, I want to reduce 2.758ns,how? thank you!

(Z60TQC82GXXF8)0ZGHNSVM.png8VH($311[J$D578A)(N$HYN.png

0 Kudos
Reply
8 Replies
dpaul24
Scholar
Scholar
529 Views
Registered: ‎08-07-2014

@zengqh ,

The net delay cannot be helped because it needs to be connected from the clock pin to the location where it is needed.

As an alternative, it might help if it is possible for you to connect the clock input to another clock capable pin whose location is much closer.

------------FPGA enthusiast------------
Consider giving "Kudos" if you like my answer. Please mark my post "Accept as solution" if my answer has solved your problem

zengqh
Adventurer
Adventurer
518 Views
Registered: ‎01-10-2019

@dpaul24
I have to use this synchronous clock, can I add buffer to reduce, or whatever,
0 Kudos
Reply
dpaul24
Scholar
Scholar
511 Views
Registered: ‎08-07-2014

@zengqh ,

I have to use this synchronous clock, can I add buffer to reduce, or whatever,

Do you mean to say that since this is a sync clock, you want to align the data associated with it?

If this is so, then yes, can be done. But you do not add a buffer to the clock net/path. Let the clock net be as it is.

What you can use is an IDELAY module for the data path, giving it the requisite delay, so that your clock and data gets aligned.

 

------------FPGA enthusiast------------
Consider giving "Kudos" if you like my answer. Please mark my post "Accept as solution" if my answer has solved your problem

surajc
Xilinx Employee
Xilinx Employee
498 Views
Registered: ‎01-30-2019

Hi @zengqh 
The delay which you are seeing is the routing delay of the net which goes from BUFG -> FDCE/C.

For now, it seems that the placer and router found this placement and routing optimal for your path as per the timing requirements. 
Why do you want to reduce this delay?

To reduce delay:
You can use floor planning to constrain the FDCE near to the BUFG  See https://www.xilinx.com/video/hardware/design-analysis-floorplanning-with-vivado.html
You can also use different placer and router directives so that tool can use different algorithms and see if that reduces the delay 

 

zengqh
Adventurer
Adventurer
437 Views
Registered: ‎01-10-2019

@dpaul24,
thank you for you answer!The data path in module,I think it isn't use IDELY.So I reduce frequency.
0 Kudos
Reply
zengqh
Adventurer
Adventurer
436 Views
Registered: ‎01-10-2019

@surajc.
Thank you for your answer.I think you are right,but I use pblock to fix position,I reduce frequency to meet the timing.
0 Kudos
Reply
dpaul24
Scholar
Scholar
427 Views
Registered: ‎08-07-2014

@zengqh ,

The data path in module,I think it isn't use IDELY.

I know, perhaps you did not understand what I meant. I wanted to say that if you still (the clock path suffering a delay due to net routing) want to make your clk and data synchronous, then you can insert an IDELAY module in your data path which will compensate the clock path delay.

So I reduce frequency.

If you are flexible with your clock it is your choice. What I told you is an universal way to synchronize clock and data inside the FPGA, when the clock frequency cannot be changed.

------------FPGA enthusiast------------
Consider giving "Kudos" if you like my answer. Please mark my post "Accept as solution" if my answer has solved your problem

surajc
Xilinx Employee
Xilinx Employee
422 Views
Registered: ‎01-30-2019

Hi @zengqh 

I use pblock to fix position,I reduce frequency to meet the timing.
can you elaborate on this statement? 

Also If the FDRE are less then you can use CLOCK_LOW_FANOUT on them to constrain them to a Clock Region. This might reduce the distance between the BUFG and FDRE's. Please give this a try