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Observer eita
Observer
1,705 Views
Registered: ‎12-21-2017

How to solve [Place 30-675] in xczu3eg??

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Hi all.

 

I have a problems for PnR with vivado implementation.

How can I solve this error?

 

I was designed serdes with IBUFGDS on 7series ZYNQ FPGA.

Now, I want to replace FPGA device 7series to Ultra scale+ MPSoC.

My device is xczu3eg on  avnet's ultrazed_eg_iocc board.

 

I connect IBUFGDS on RTL below.

IBUFDS #(.DQS_BIAS("FALSE"))
iob_clk_in(.I(clkin_p),.IB(clkin_n),.O(rx_clk_in_p));
BUFG iserdes_cm_bf(.I(rx_clk_in_p),.O(rx_clk_in_pc));

And start implement, become this error message.

[Place 30-675] 
Sub-optimal placement for a global clock-capable IO pin and BUFG pair.If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING.  However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
< set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets /U_user_top/iob_clk_in/O] >

/U_user_top/iob_clk_in/IBUFCTRL_INST (IBUFCTRL.O) is locked to IOB_X2Y84
/U_user_top/iserdes_cm_bf (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y43

The above error could possibly be related to other connected instances. Following is a list of 
all the related clock rules and their respective instances.

Clock Rule: rule_floating_clklds_in_half_column
Status: PASS 
Rule Description: Floating ISERDESs/OSERDESs/IDELAYs/ODELAYs (ones without an associated IOB) loads
of global clock buffers like  BUFGCE/BUFGCTRL/BUFGCE_DIV must be placed such that there are not more
than 6 clock nets in an IO half bank
/U_user_top/iserdes_cm (ISERDESE3.CLK) is locked to BITSLICE_RX_TX_X0Y84

Clock Rule: rule_floating_clklds_in_half_column
Status: PASS 
Rule Description: Floating ISERDESs/OSERDESs/IDELAYs/ODELAYs (ones without an associated IOB) loads
of global clock buffers like  BUFGCE/BUFGCTRL/BUFGCE_DIV must be placed such that there are not more
than 6 clock nets in an IO half bank
/U_user_top/iserdes_cm (ISERDESE3.CLKDIV) is locked to BITSLICE_RX_TX_X0Y84

Clock Rule: rule_floating_clklds_in_half_column
Status: PASS 
Rule Description: Floating ISERDESs/OSERDESs/IDELAYs/ODELAYs (ones without an associated IOB) loads
of global clock buffers like  BUFGCE/BUFGCTRL/BUFGCE_DIV must be placed such that there are not more
than 6 clock nets in an IO half bank
/U_user_top/iserdes_cm (ISERDESE3.CLK_B) is locked to BITSLICE_RX_TX_X0Y84

Clock Rule: rule_bufgce_bufg_conflict
Status: PASS 
Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be
used at the same time
and /U_user_top/iserdes_cm_bf (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X0Y43

Also error message become on generate bit stream.

[DRC RTSTAT-2] Partially routed nets: 1 net(s) are partially routed. The problem bus(es) and/or net(s) are /U_user_top/iob_clk_in/O.
[Vivado 12-1345] Error(s) found during DRC. Bitgen not run.

After synthesis design connection below.

prop.gif

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1 Solution

Accepted Solutions
Xilinx Employee
Xilinx Employee
2,293 Views
Registered: ‎05-08-2012

Re: How to solve [Place 30-675] in xczu3eg??

Jump to solution

Hi @eita. If the CLOCK_DEDICATED_ROUTE FALSE is not working, this could be looked at with an uploaded DCP. Otherwise, did the new change resolve the issue? If so, please mark this post as resolved.

6 Replies
Moderator
Moderator
1,702 Views
Registered: ‎01-16-2013

Re: How to solve [Place 30-675] in xczu3eg??

Jump to solution

@eita,

 

Can you please share the post opt dcp file?

 

--Syed

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Did you check our new quick reference timing closure guide (UG1292)?
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Observer eita
Observer
1,622 Views
Registered: ‎12-21-2017

Re: How to solve [Place 30-675] in xczu3eg??

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Hi @syedz.

 

I must apologize for the delay.

 

I attached dcp file.

 

 

 

 

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Xilinx Employee
Xilinx Employee
1,604 Views
Registered: ‎05-08-2012

Re: How to solve [Place 30-675] in xczu3eg??

Jump to solution

Hi @eita. There are two issues here:

  • The M2/M1 package pins are general IO and not Clock Capable pins which leads to the Place 30-675. Choosing different package pins or setting CLOCK_DEDICATED_ROUTE FALSE (not advised) will avoid the error.
  • The IBUFDS is connecting to both an IDELAYE3/IDATAIN and the BUFG. This leads to a REQP-1945 DRC error which indicates that this is an unroutable connection. The IBUFDS can only connect to IDELAYE3/IDATAIN, and not the BUFG.

REQP #1 Error The IDELAYE3 cell U_bosmina_top/U_user_top/U_sen_if/U_despara_top/U_despara_decoder/U_des/idelay_cm_m pin U_bosmina_top/U_user_top/U_sen_if/U_despara_top/U_despara_decoder/U_des/idelay_cm_m/IDATAIN attached to net U_bosmina_top/U_user_top/U_sen_if/U_despara_top/U_despara_decoder/U_des/rx_clk_in_p is also connected to other loads. This is not routable due to conflicting attributes for the net.

Observer eita
Observer
1,538 Views
Registered: ‎12-21-2017

Re: How to solve [Place 30-675] in xczu3eg??

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Hi @marcb.

 

Thank you for reply.


I added CLOCK_DEDICATED_ROUTE FALSE into constraint, but the error still become.
This is not advised method, So I take another measures.

So I will chose another package pins.

Also I refine connection of IBUFDS's output, and check results.
I think this error caused by IBUFDS's connections, by the some physical place ment constraint.

 

Regards.

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Xilinx Employee
Xilinx Employee
2,294 Views
Registered: ‎05-08-2012

Re: How to solve [Place 30-675] in xczu3eg??

Jump to solution

Hi @eita. If the CLOCK_DEDICATED_ROUTE FALSE is not working, this could be looked at with an uploaded DCP. Otherwise, did the new change resolve the issue? If so, please mark this post as resolved.

Observer eita
Observer
1,493 Views
Registered: ‎12-21-2017

Re: How to solve [Place 30-675] in xczu3eg??

Jump to solution

Hi @marcb.

 

I was changed clock pin assign, and it's solved.
Thank you for advise.

 

Regards.

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